Running: C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o X:/My Documents/ec311/ec311-lab4/TEST_Countdown_isim_beh.exe -prj X:/My Documents/ec311/ec311-lab4/TEST_Countdown_beh.prj work.TEST_Countdown work.glbl ISim O.76xd (signature 0xc3576ebc) Number of CPUs detected in this system: 2 Turning on mult-threading, number of parallel sub-compilation jobs: 4 Determining compilation order of HDL files Analyzing Verilog file "X:/My Documents/ec311/ec311-lab4/Countdown.v" into library work WARNING:HDLCompiler:751 - "X:/My Documents/ec311/ec311-lab4/Countdown.v" Line 29: Redeclaration of ansi port t is not allowed Analyzing Verilog file "X:/My Documents/ec311/ec311-lab4/TEST_Countdown.v" into library work Analyzing Verilog file "C:/Xilinx/13.3/ISE_DS/ISE//verilog/src/glbl.v" into library work Starting static elaboration Completed static elaboration Compiling module Countdown Compiling module TEST_Countdown Compiling module glbl Time Resolution for simulation is 1ps. Waiting for 1 sub-compilation(s) to finish... Compiled 3 Verilog Units Built simulation executable X:/My Documents/ec311/ec311-lab4/TEST_Countdown_isim_beh.exe Fuse Memory Usage: 26940 KB Fuse CPU Usage: 467 ms