"/home/michael/Documents/School/EC311/lab4/SevSegDisp.v" Line 27: Redeclaration of ansi port out is not allowed "/home/michael/Documents/School/EC311/lab4/Increment.v" Line 26: Redeclaration of ansi port value is not allowed "/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 30: Redeclaration of ansi port AN is not allowed "/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 31: Redeclaration of ansi port result is not allowed "/home/michael/Documents/School/EC311/lab4/Countdown.v" Line 29: Redeclaration of ansi port t is not allowed "/home/michael/Documents/School/EC311/lab4/ClockDivider.v" Line 28: Redeclaration of ansi port clk_out is not allowed "/home/michael/Documents/School/EC311/lab4/Bin2BCD.v" Line 28: Redeclaration of ansi port one is not allowed "/home/michael/Documents/School/EC311/lab4/BCD2Bin.v" Line 28: Redeclaration of ansi port bin is not allowed "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 31: Redeclaration of ansi port ssd is not allowed "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 32: Redeclaration of ansi port AN is not allowed "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 54: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 55: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 53: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 66: Size mismatch in connection of port <hun>. Formal port size is 4-bit while actual signal size is 32-bit.