From 5d32d4ca9aaf2000e05503457bed1b8f04ca6d62 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Wed, 28 Mar 2012 09:58:28 -0400 Subject: initial commit --- Bin2BCD.v | 57 ++++++ ClockDivider.v | 47 +++++ DisplayController.v | 65 +++++++ DisplayController_summary.html | 79 ++++++++ FIRController.v | 46 +++++ FIRController_summary.html | 79 ++++++++ FIRFilter.v | 42 ++++ SevSegDisp.v | 45 +++++ _xmsgs/pn_parser.xmsgs | 15 ++ iseconfig/FIRController.xreport | 215 +++++++++++++++++++++ iseconfig/lab5.projectmgr | 77 ++++++++ lab5.gise | 28 +++ lab5.xise | 418 ++++++++++++++++++++++++++++++++++++++++ 13 files changed, 1213 insertions(+) create mode 100644 Bin2BCD.v create mode 100644 ClockDivider.v create mode 100644 DisplayController.v create mode 100644 DisplayController_summary.html create mode 100644 FIRController.v create mode 100644 FIRController_summary.html create mode 100644 FIRFilter.v create mode 100644 SevSegDisp.v create mode 100644 _xmsgs/pn_parser.xmsgs create mode 100644 iseconfig/FIRController.xreport create mode 100644 iseconfig/lab5.projectmgr create mode 100644 lab5.gise create mode 100644 lab5.xise diff --git a/Bin2BCD.v b/Bin2BCD.v new file mode 100644 index 0000000..7af8725 --- /dev/null +++ b/Bin2BCD.v @@ -0,0 +1,57 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 10:16:12 03/16/2012 +// Design Name: +// Module Name: Bin2BCD +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Bin2BCD( + input [15:0] bin, + output [3:0] one, + output [3:0] ten, + output [3:0] hun, + output [3:0] thous + ); + +reg [3:0] one, ten, hun, thous; +reg [31:0] work; +reg [3:0] i; + +always @( bin ) begin + hun = 0; ten = 0; one = 0; + work = {thous, hun, ten, one, bin}; + + for (i = 0; i < 15; i = i +1) begin + work = work << 1; + if (work[31:28] >= 5) + work[31:28] = work[31:28] + 4'd3; + if (work[27:24] >= 5) + work[27:24] = work[27:24] + 4'd3; + if (work[23:20] >= 5) + work[23:20] = work[23:20] + 4'd3; + if (work[19:16] >= 5) + work[19:16] = work[19:16] + 4'd3; + end + + work = work << 1; + + thous = work[31:28]; + hun = work[27:24]; + ten = work[23:20]; + one = work[19:16]; +end + +endmodule diff --git a/ClockDivider.v b/ClockDivider.v new file mode 100644 index 0000000..7ced5a7 --- /dev/null +++ b/ClockDivider.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:24:11 03/16/2012 +// Design Name: +// Module Name: ClockDivider +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ClockDivider( + input clk_in, + input rst, + input [23:0] count, + output clk_out + ); + +reg clk_out = 0; +reg [23:0] c = 0; + +always @(posedge clk_in or posedge rst) begin + if (rst == 1) begin + c = 0; + clk_out = 0; + end else if (c == count) begin + clk_out = ~clk_out; + c = 0; + end else begin + c = c + 24'd1; + end + + +end + + + +endmodule diff --git a/DisplayController.v b/DisplayController.v new file mode 100644 index 0000000..6da8227 --- /dev/null +++ b/DisplayController.v @@ -0,0 +1,65 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:52:48 03/27/2012 +// Design Name: +// Module Name: DisplayController +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DisplayController( + input [3:0] A, + input [3:0] B, + input [3:0] C, + input [3:0] D, + input clk, + input rst, + output [6:0] ssd, + output [3:0] AN + ); + + +reg [6:0] ssd; +reg [3:0] AN; + +wire clkdiv; +reg [1:0] w = 2'd0; + +ClockDivider cdiv(.clk_out(clkdiv), .rst(rst), .clk_in(clk), .count(500_000)); + +wire [6:0] o1, o2, o3, o4; + +SevSegDisp d1(.result(o1), .A(A)); +SevSegDisp d2(.result(o2), .A(B)); +SevSegDisp d3(.result(o3), .A(C)); +SevSegDisp d4(.result(o4), .A(D)); + +always @(posedge clkdiv) begin + w <= w + 2'd1; + case (w) + 2'b00: AN <= 4'b1110; + 2'b01: AN <= 4'b1101; + 2'b10: AN <= 4'b1011; + 2'b11: AN <= 4'b0111; + endcase + case (w) + 2'b00: ssd <= o1; + 2'b01: ssd <= o2; + 2'b10: ssd <= o3; + 2'b11: ssd <= o4; + endcase +end + + +endmodule diff --git a/DisplayController_summary.html b/DisplayController_summary.html new file mode 100644 index 0000000..e3bd536 --- /dev/null +++ b/DisplayController_summary.html @@ -0,0 +1,79 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FIRController Project Status
Project File:lab5.xiseParser Errors:X 1 Error
Module Name:DisplayControllerImplementation State:New
Target Device:xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 13.4
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 03/27/2012 - 16:53:37
+ \ No newline at end of file diff --git a/FIRController.v b/FIRController.v new file mode 100644 index 0000000..c71ea12 --- /dev/null +++ b/FIRController.v @@ -0,0 +1,46 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:51:34 03/27/2012 +// Design Name: +// Module Name: FIRController +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module FIRController( + input clk, + input load, + input rst, + input [7:0] yin, + output [6:0] ssd, + output [3:0] AN + ); + +wire [15:0] yout; + +FIRFilter ff(.yin(yin), .yout(yout)); + +wire [3:0] one, ten, hun, thous; + +Bin2BCD b2bcd(.bin(yout), .thous(thous), .hun(hun), .ten(ten), .one(one)); + +wire [6:0] ssdw; +wire [3:0] ANw; + +DisplayController dc(.A(thous), .B(hun), .C(ten), .D(one), .clk(clk), .rst(rst), .ssd(ssdw), .AN(ANw)); + +assign ssd = ssdw; +assign AN = ANw; + +endmodule diff --git a/FIRController_summary.html b/FIRController_summary.html new file mode 100644 index 0000000..4f59e04 --- /dev/null +++ b/FIRController_summary.html @@ -0,0 +1,79 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
FIRController Project Status
Project File:lab5.xiseParser Errors: No Errors
Module Name:FIRControllerImplementation State:New
Target Device:xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 13.4
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 03/27/2012 - 15:51:36
+ \ No newline at end of file diff --git a/FIRFilter.v b/FIRFilter.v new file mode 100644 index 0000000..dada832 --- /dev/null +++ b/FIRFilter.v @@ -0,0 +1,42 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:36:01 03/27/2012 +// Design Name: +// Module Name: FIRFilter +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module FIRFilter( + input [7:0] yin, + output [15:0] yout, + input load, + input rst + ); + +reg [15:0] yout; + +reg [15:0] yold1; +reg [15:0] yold2; + +always @(*) begin + yout = 20*yin + 15*yold1 + 10*yold2; +end + +always @(load) begin + yold2 = yold1; + yold1 = yin; +end + +endmodule diff --git a/SevSegDisp.v b/SevSegDisp.v new file mode 100644 index 0000000..8d2c3b1 --- /dev/null +++ b/SevSegDisp.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:01:14 03/16/2012 +// Design Name: +// Module Name: SevSegDisp +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module SevSegDisp( + input [3:0] A, + output [6:0] result + ); + +reg [6:0] result = 0; + +always @ ( * ) begin + case ( A ) + 4'b0000 : result = 7'b0000001; + 4'b0001 : result = 7'b1001111; + 4'b0010 : result = 7'b0010010; + 4'b0011 : result = 7'b0000110; + 4'b0100 : result = 7'b1001100; + 4'b0101 : result = 7'b0100100; + 4'b0110 : result = 7'b0100000; + 4'b0111 : result = 7'b0001111; + 4'b1000 : result = 7'b0000000; + 4'b1001 : result = 7'b0001100; + default : result = 7'b0011010; + endcase +end + +endmodule diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..278dafe --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ + + + + + + + + + + +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab5/DisplayController.v" into library work + + + + diff --git a/iseconfig/FIRController.xreport b/iseconfig/FIRController.xreport new file mode 100644 index 0000000..80763e1 --- /dev/null +++ b/iseconfig/FIRController.xreport @@ -0,0 +1,215 @@ + + +
+ 2012-03-27T16:33:33 + DisplayController + Unknown + /home/michael/Documents/School/EC311/lab5/iseconfig/FIRController.xreport + /home/michael/Documents/School/EC311/lab5 + 2012-03-27T16:33:33 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/iseconfig/lab5.projectmgr b/iseconfig/lab5.projectmgr new file mode 100644 index 0000000..ce403c0 --- /dev/null +++ b/iseconfig/lab5.projectmgr @@ -0,0 +1,77 @@ + + + + + + + + + 2 + + + dc - DisplayController (/home/michael/Documents/School/EC311/lab5/DisplayController.v) + + 1 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000155000000020000000000000000000000000200000064ffffffff000000810000000300000002000001550000000100000003000000000000000100000003 + true + dc - DisplayController (/home/michael/Documents/School/EC311/lab5/DisplayController.v) + + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000154000000010000000100000000000000000000000064ffffffff000000810000000000000001000001540000000100000000 + false + + + + + 1 + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000287000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004a00000001000000000000002800000001000000000000007900000001000000000000019c0000000100000000 + false + + + + + 1 + work + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000117000000010001000100000000000000000000000064ffffffff000000810000000000000001000001170000000100000000 + false + work + + + + 1 + Configure Target Device + Design Utilities + Implement Design + Synthesize - XST + User Constraints + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000154000000010000000100000000000000000000000064ffffffff000000810000000000000001000001540000000100000000 + false + + + 000000ff00000000000000020000013f0000012001000000060100000002 + Implementation + diff --git a/lab5.gise b/lab5.gise new file mode 100644 index 0000000..ffdbb97 --- /dev/null +++ b/lab5.gise @@ -0,0 +1,28 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + diff --git a/lab5.xise b/lab5.xise new file mode 100644 index 0000000..3c999cf --- /dev/null +++ b/lab5.xise @@ -0,0 +1,418 @@ + + + +
+ + + + + + + + +
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