From 9540811daaffad7811475ea584333ab633ba8508 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Thu, 29 Mar 2012 16:17:45 -0400 Subject: yay --- TEST_Bin2BCD.v | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 TEST_Bin2BCD.v (limited to 'TEST_Bin2BCD.v') diff --git a/TEST_Bin2BCD.v b/TEST_Bin2BCD.v new file mode 100644 index 0000000..7561bf6 --- /dev/null +++ b/TEST_Bin2BCD.v @@ -0,0 +1,60 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:26:38 03/29/2012 +// Design Name: Bin2BCD +// Module Name: /home/michael/Documents/School/EC311/lab5/TEST_Bin2BCD.v +// Project Name: lab5 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Bin2BCD +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_Bin2BCD; + + // Inputs + reg [15:0] bin; + + // Outputs + wire [3:0] one; + wire [3:0] ten; + wire [3:0] hun; + wire [3:0] thous; + + // Instantiate the Unit Under Test (UUT) + Bin2BCD uut ( + .bin(bin), + .one(one), + .ten(ten), + .hun(hun), + .thous(thous) + ); + + initial begin + // Initialize Inputs + bin = 0; + + // Wait 100 ns for global reset to finish + #100; + bin = 7; #50; + bin = 16;#50; + bin = 217;#50; + bin = 1839; #50; + // Add stimulus here + + end + +endmodule + -- cgit v1.2.3