`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:16:12 03/16/2012 
// Design Name: 
// Module Name:    Bin2BCD 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Bin2BCD(
    input [15:0] bin,
    output [3:0] one,
    output [3:0] ten,
    output [3:0] hun,
	 output [3:0] thous
    );

reg [3:0] one, ten, hun, thous;
reg [31:0] work;
reg [3:0] i;

always @( bin ) begin
	hun = 0; ten = 0; one = 0;
	work = {thous, hun, ten, one, bin};

	for (i = 0; i < 15; i = i +1) begin
		work = work << 1;
		if (work[31:28] >= 5)
			work[31:28] = work[31:28] + 4'd3;
		if (work[27:24] >= 5)
			work[27:24] = work[27:24] + 4'd3;
		if (work[23:20] >= 5)
			work[23:20] = work[23:20] + 4'd3;
		if (work[19:16] >= 5) 
			work[19:16] = work[19:16] + 4'd3;
	end
	
	work = work << 1;
	
	thous = work[31:28];
	hun = work[27:24];
	ten = work[23:20];	
	one = work[19:16];
end

endmodule