`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    15:51:34 03/27/2012 
// Design Name: 
// Module Name:    FIRController 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module FIRController(
	input clk,
	input load,
	input rst,
	input [7:0] yin,
	output [6:0] ssd,
	output [3:0] AN
    );

wire [15:0] yout;

FIRFilter ff(.yin(yin), .yout(yout));

wire [3:0] one, ten, hun, thous;

Bin2BCD b2bcd(.bin(yout), .thous(thous), .hun(hun), .ten(ten), .one(one));

wire [6:0] ssdw;
wire [3:0] ANw;

DisplayController dc(.A(thous), .B(hun), .C(ten), .D(one), .clk(clk), .rst(rst), .ssd(ssdw), .AN(ANw));

assign ssd = ssdw;
assign AN = ANw;

endmodule