`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:36:01 03/27/2012 
// Design Name: 
// Module Name:    FIRFilter 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module FIRFilter(
    input [7:0] yin,
    output [15:0] yout,
    input load,
    input rst
    );

reg [15:0] yout;

reg [15:0] yold1=0;
reg [15:0] yold2=0;

always @(yin, yold1, yold2, rst) begin
	if (rst)
		yout = 0;
	else
		yout = 20*yin + 15*yold1 + 10*yold2;
end

always @(posedge load, posedge rst) begin
	if (rst) begin
		yold1 = 0;
		yold2 = 0;
	end else begin
		yold2 = yold1;
		yold1 = yin;
	end
end

endmodule