`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:17:59 03/29/2012
// Design Name:   DisplayController
// Module Name:   /home/michael/Documents/School/EC311/lab5/TEST_DisplayController.v
// Project Name:  lab5
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: DisplayController
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TEST_DisplayController;

	// Inputs
	reg [3:0] A;
	reg [3:0] B;
	reg [3:0] C;
	reg [3:0] D;
	reg clk;
	reg rst;

	// Outputs
	wire [6:0] ssd;
	wire [3:0] AN;

	// Instantiate the Unit Under Test (UUT)
	DisplayController uut (
		.A(A), 
		.B(B), 
		.C(C), 
		.D(D), 
		.clk(clk), 
		.rst(rst), 
		.ssd(ssd), 
		.AN(AN)
	);

	initial begin
		// Initialize Inputs
		A = 0;
		B = 0;
		C = 0;
		D = 0;
		clk = 0;
		rst = 0;

		// Wait 100 ns for global reset to finish
		#100;
      A=4'd3;
		B=4'd0;
		C=4'd7;
		D=4'd9;
		while (1) begin
			clk = ~clk; #1;
		end
		// Add stimulus here

	end
      
endmodule