From c5c3101483a4c2facd67f514f0c320b4192f5844 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Thu, 5 Apr 2012 15:53:47 -0400 Subject: lab6 --- ClockDivider.v | 47 ++ Detector.v | 66 +++ Detector_summary.html | 79 +++ DisplayController.v | 48 ++ FSMController.v | 63 +++ SevSegDisp.v | 45 ++ TEST_Detector.v | 66 +++ TEST_Detector_beh.prj | 3 + TEST_Detector_isim_beh.exe | Bin 0 -> 21792 bytes TEST_Detector_isim_beh.wdb | Bin 0 -> 144 bytes _xmsgs/pn_parser.xmsgs | 15 + debouncer.v | 56 +++ detector.wcfg | 43 ++ fuse.log | 24 + fuse.xmsgs | 15 + fuseRelaunch.cmd | 1 + iseconfig/Detector.xreport | 215 ++++++++ iseconfig/lab6.projectmgr | 58 +++ isim.cmd | 3 + isim.log | 37 ++ .../ISimEngine-DesignHierarchy.dbg | Bin 0 -> 4736 bytes .../TEST_Detector_isim_beh.exe | Bin 0 -> 16512 bytes isim/TEST_Detector_isim_beh.exe.sim/isimcrash.log | 0 isim/TEST_Detector_isim_beh.exe.sim/isimkernel.log | 10 + isim/TEST_Detector_isim_beh.exe.sim/netId.dat | Bin 0 -> 84 bytes isim/TEST_Detector_isim_beh.exe.sim/tmp_save/_1 | Bin 0 -> 2678 bytes .../work/TEST_Detector_isim_beh.exe_main.c | 36 ++ .../work/TEST_Detector_isim_beh.exe_main.lin64.o | Bin 0 -> 2448 bytes .../work/m_13872111861810629931_1087962131.c | 547 +++++++++++++++++++++ .../work/m_13872111861810629931_1087962131.didat | Bin 0 -> 3112 bytes .../work/m_13872111861810629931_1087962131.lin64.o | Bin 0 -> 7992 bytes .../work/m_14253225476704866645_1235880303.c | 286 +++++++++++ .../work/m_14253225476704866645_1235880303.didat | Bin 0 -> 3440 bytes .../work/m_14253225476704866645_1235880303.lin64.o | Bin 0 -> 5176 bytes .../work/m_16541823861846354283_2073120511.c | 337 +++++++++++++ .../work/m_16541823861846354283_2073120511.didat | Bin 0 -> 5556 bytes .../work/m_16541823861846354283_2073120511.lin64.o | Bin 0 -> 5232 bytes isim/isim_usage_statistics.html | 5 + isim/lockfile | 0 isim/pn_info | 1 + isim/work/@detector.sdb | Bin 0 -> 4098 bytes isim/work/@t@e@s@t_@detector.sdb | Bin 0 -> 3126 bytes isim/work/glbl.sdb | Bin 0 -> 5172 bytes lab6.gise | 102 ++++ lab6.xise | 387 +++++++++++++++ xilinxsim.ini | 1 + 46 files changed, 2596 insertions(+) create mode 100644 ClockDivider.v create mode 100644 Detector.v create mode 100644 Detector_summary.html create mode 100644 DisplayController.v create mode 100644 FSMController.v create mode 100644 SevSegDisp.v create mode 100644 TEST_Detector.v create mode 100644 TEST_Detector_beh.prj create mode 100755 TEST_Detector_isim_beh.exe create mode 100644 TEST_Detector_isim_beh.wdb create mode 100644 _xmsgs/pn_parser.xmsgs create mode 100644 debouncer.v create mode 100644 detector.wcfg create mode 100644 fuse.log create mode 100644 fuse.xmsgs create mode 100644 fuseRelaunch.cmd create mode 100644 iseconfig/Detector.xreport create mode 100644 iseconfig/lab6.projectmgr create mode 100644 isim.cmd create mode 100644 isim.log create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg create mode 100755 isim/TEST_Detector_isim_beh.exe.sim/TEST_Detector_isim_beh.exe create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/isimcrash.log create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/isimkernel.log create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/netId.dat create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/tmp_save/_1 create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.c create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.lin64.o create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.c create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.didat create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.lin64.o create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.c create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.didat create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/work/m_14253225476704866645_1235880303.lin64.o create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat create mode 100644 isim/TEST_Detector_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o create mode 100644 isim/isim_usage_statistics.html create mode 100644 isim/lockfile create mode 100644 isim/pn_info create mode 100644 isim/work/@detector.sdb create mode 100644 isim/work/@t@e@s@t_@detector.sdb create mode 100644 isim/work/glbl.sdb create mode 100644 lab6.gise create mode 100644 lab6.xise create mode 100644 xilinxsim.ini diff --git a/ClockDivider.v b/ClockDivider.v new file mode 100644 index 0000000..7ced5a7 --- /dev/null +++ b/ClockDivider.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:24:11 03/16/2012 +// Design Name: +// Module Name: ClockDivider +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ClockDivider( + input clk_in, + input rst, + input [23:0] count, + output clk_out + ); + +reg clk_out = 0; +reg [23:0] c = 0; + +always @(posedge clk_in or posedge rst) begin + if (rst == 1) begin + c = 0; + clk_out = 0; + end else if (c == count) begin + clk_out = ~clk_out; + c = 0; + end else begin + c = c + 24'd1; + end + + +end + + + +endmodule diff --git a/Detector.v b/Detector.v new file mode 100644 index 0000000..f1bba2a --- /dev/null +++ b/Detector.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:38:26 04/05/2012 +// Design Name: +// Module Name: Detector +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Detector( + input inp, + input clk, + input rst, + output result, + output [1:0] state + ); + +reg [1:0] state; +reg [1:0] nextstate; +reg result; + +initial begin + state = 0; + result = 0; +end + +always @(posedge clk or posedge rst) begin + if (rst) begin + state <= 0; + end else begin + state <= nextstate; + end +end + +always @(*) begin + case (state) + 2'b00: nextstate = inp ? 2'b01 : 2'b00; + 2'b01: nextstate = inp ? 2'b10 : 2'b00; + 2'b10: nextstate = inp ? 2'b11 : 2'b00; + 2'b11: nextstate = inp ? 2'b11 : 2'b00; + default: nextstate = 2'b00; + endcase +end + +always @(state) begin + case (state) + 2'b00: result = 0; + 2'b01: result = 0; + 2'b10: result = 0; + 2'b11: result = 1; + default: result = 0; + endcase +end + +endmodule diff --git a/Detector_summary.html b/Detector_summary.html new file mode 100644 index 0000000..559c488 --- /dev/null +++ b/Detector_summary.html @@ -0,0 +1,79 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Detector Project Status
Project File:lab6.xiseParser Errors: No Errors
Module Name:DetectorImplementation State:New
Target Device:xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 13.4
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 04/05/2012 - 15:00:11
+ \ No newline at end of file diff --git a/DisplayController.v b/DisplayController.v new file mode 100644 index 0000000..9e4cc66 --- /dev/null +++ b/DisplayController.v @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:03:47 03/16/2012 +// Design Name: +// Module Name: DisplayController +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DisplayController( + input [3:0] A, + input [3:0] B, + input clk_in, + input rst, + output [6:0] result, + output [3:0] AN + ); + +reg [3:0] AN; +reg [6:0] result = 0; + +wire [6:0] ssd1; +wire [6:0] ssd2; + +reg prev = 0; + +SevSegDisp d1(.A(A), .result(ssd1)); +SevSegDisp d2(.A(B), .result(ssd2)); + +always @( posedge clk_in ) begin + prev <= ~prev; + result <= prev ? ssd1 : ssd2; + AN <= { ~prev, 2'b11, prev }; +end + + +endmodule diff --git a/FSMController.v b/FSMController.v new file mode 100644 index 0000000..65cd70b --- /dev/null +++ b/FSMController.v @@ -0,0 +1,63 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:33:05 04/05/2012 +// Design Name: +// Module Name: FSMController +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module FSMController( + input clk, + input btn, + input [7:0] pattern, + input rst, + output [6:0] ssd, + output [3:0] an + ); +reg [6:0] ssd; +reg [3:0] an; + +reg [2:0] idx; + +wire inp; +wire dbbtn; +wire dbclk; +wire dpclk; +wire res; +wire [1:0] state; +wire [6:0] ssdw; +wire [3:0] anw; + +ClockDivider cdiv(.count(100), .rst(rst), .clk_in(clk), .clk_out(dbclk)); +ClockDivider dclk(.count(75000), .rst(rst), .clk_in(clk), .clk_out(dpclk)); +debouncer dbclk(.clk_1M(dbclk), .rst(rst), .din(btn), .dout(dbbtn)); + +Detector d(.inp(inp), .clk(dbbtn), .rst(rst), .result(res), .state(state)); + +DisplayController dc(.A({2'b00, state}), .B({3'b000, res}), .rst(rst), .clk_in(dpclk), .result(ssdw), .AN(anw)); + +initial begin + idx = 0; +end + +assign ssd = ssdw; +assign an = anw; + +always @(posedge clk) begin + idx = idx + 1; + inp <= inp[7-idx]; +end + +endmodule diff --git a/SevSegDisp.v b/SevSegDisp.v new file mode 100644 index 0000000..8d2c3b1 --- /dev/null +++ b/SevSegDisp.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:01:14 03/16/2012 +// Design Name: +// Module Name: SevSegDisp +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module SevSegDisp( + input [3:0] A, + output [6:0] result + ); + +reg [6:0] result = 0; + +always @ ( * ) begin + case ( A ) + 4'b0000 : result = 7'b0000001; + 4'b0001 : result = 7'b1001111; + 4'b0010 : result = 7'b0010010; + 4'b0011 : result = 7'b0000110; + 4'b0100 : result = 7'b1001100; + 4'b0101 : result = 7'b0100100; + 4'b0110 : result = 7'b0100000; + 4'b0111 : result = 7'b0001111; + 4'b1000 : result = 7'b0000000; + 4'b1001 : result = 7'b0001100; + default : result = 7'b0011010; + endcase +end + +endmodule diff --git a/TEST_Detector.v b/TEST_Detector.v new file mode 100644 index 0000000..8f038f8 --- /dev/null +++ b/TEST_Detector.v @@ -0,0 +1,66 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:01:00 04/05/2012 +// Design Name: Detector +// Module Name: /home/michael/Documents/School/EC311/lab6/TEST_Detector.v +// Project Name: lab6 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Detector +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_Detector; + + // Inputs + reg inp; + reg clk; + reg rst; + + // Outputs + wire result; + wire [1:0] state; + + // Instantiate the Unit Under Test (UUT) + Detector uut ( + .inp(inp), + .clk(clk), + .rst(rst), + .result(result), + .state(state) + ); + + reg [19:0] pattern = 20'b11010111011111110110; + reg [15:0] i; + initial begin + // Initialize Inputs + inp = 0; + clk = 0; + rst = 0; + i = 0; + + // Wait 100 ns for global reset to finish + #50; + + // Add stimulus here + for (i = 0; i < 20; i = i + 1) begin + inp = pattern[19-i]; + clk = ~clk; #5; + clk = ~clk; #5; + end + end + +endmodule + diff --git a/TEST_Detector_beh.prj b/TEST_Detector_beh.prj new file mode 100644 index 0000000..725319e --- /dev/null +++ b/TEST_Detector_beh.prj @@ -0,0 +1,3 @@ +verilog work "Detector.v" +verilog work "TEST_Detector.v" +verilog work "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/TEST_Detector_isim_beh.exe b/TEST_Detector_isim_beh.exe new file mode 100755 index 0000000..beb9ccd Binary files /dev/null and b/TEST_Detector_isim_beh.exe differ diff --git a/TEST_Detector_isim_beh.wdb b/TEST_Detector_isim_beh.wdb new file mode 100644 index 0000000..093e2eb Binary files /dev/null and b/TEST_Detector_isim_beh.wdb differ diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..54b96d0 --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ + + + + + + + + + + +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab6/FSMController.v" into library work + + + + diff --git a/debouncer.v b/debouncer.v new file mode 100644 index 0000000..d37cf6d --- /dev/null +++ b/debouncer.v @@ -0,0 +1,56 @@ +module debouncer(clk_1M, rst, din, dout); + input clk_1M; + input rst; + input din; + output dout; + + reg dout; + reg [21:0] count; + + reg sync0; // first stage of synchronizer + reg sync1; // second stage of synchronizer + + reg prev; // register for edge detection + + // synchronize input. (Synchronizers will be discussed in a future lab.) + always @(posedge clk_1M or posedge rst) begin + if (rst == 1) begin + sync0 <= 0; + sync1 <= 0; + end + else begin + sync0 <= din; + sync1 <= sync0; + end + end // always + + // perform an edge detect on the synchronized input. + always @(posedge clk_1M or posedge rst) begin + if (rst == 1) begin + prev <= 0; + end + else begin + prev <= sync1; + end + end // always + + // state machine/counter for timing the debouncing. + always @(posedge clk_1M or posedge rst) begin + if (rst == 1) begin + count <= 0; + end + else begin + if (count == 0) begin + if (sync1 == 1 && prev == 0) begin // rising edge detect + count <= 22'd100000; // 100,000 us = 100ms delay + end + dout <= 0; + end + else begin + count <= count - 22'd1; + dout <= 1; + end + end + end // always + +endmodule diff --git a/detector.wcfg b/detector.wcfg new file mode 100644 index 0000000..1310b38 --- /dev/null +++ b/detector.wcfg @@ -0,0 +1,43 @@ + + + + + + + + + + + + + + + result + result + + + state[1:0] + state[1:0] + + + inp + inp + + + clk + clk + + + rst + rst + + + pattern[15:0] + pattern[15:0] + BINARYRADIX + + + i[15:0] + i[15:0] + + diff --git a/fuse.log b/fuse.log new file mode 100644 index 0000000..44e0298 --- /dev/null +++ b/fuse.log @@ -0,0 +1,24 @@ +Running: /home/michael/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab6/TEST_Detector_beh.prj" "work.TEST_Detector" "work.glbl" +ISim O.87xd (signature 0x8ddf5b5d) +Number of CPUs detected in this system: 2 +Turning on mult-threading, number of parallel sub-compilation jobs: 4 +Determining compilation order of HDL files +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab6/Detector.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab6/Detector.v" Line 29: Redeclaration of ansi port state is not allowed +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab6/Detector.v" Line 31: Redeclaration of ansi port result is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab6/TEST_Detector.v" into library work +Analyzing Verilog file "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" into library work +Starting static elaboration +Completed static elaboration +Fuse Memory Usage: 94996 KB +Fuse CPU Usage: 1550 ms +Compiling module Detector +Compiling module TEST_Detector +Compiling module glbl +Time Resolution for simulation is 1ps. +Waiting for 1 sub-compilation(s) to finish... +Compiled 3 Verilog Units +Built simulation executable /home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe +Fuse Memory Usage: 393016 KB +Fuse CPU Usage: 1580 ms +GCC CPU Usage: 380 ms diff --git a/fuse.xmsgs b/fuse.xmsgs new file mode 100644 index 0000000..cc5dbd1 --- /dev/null +++ b/fuse.xmsgs @@ -0,0 +1,15 @@ + + + +"/home/michael/Documents/School/EC311/lab6/Detector.v" Line 29: Redeclaration of ansi port state is not allowed + + +"/home/michael/Documents/School/EC311/lab6/Detector.v" Line 31: Redeclaration of ansi port result is not allowed + + + + diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd new file mode 100644 index 0000000..f303178 --- /dev/null +++ b/fuseRelaunch.cmd @@ -0,0 +1 @@ +-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab6/TEST_Detector_beh.prj" "work.TEST_Detector" "work.glbl" diff --git a/iseconfig/Detector.xreport b/iseconfig/Detector.xreport new file mode 100644 index 0000000..2f9d918 --- /dev/null +++ b/iseconfig/Detector.xreport @@ -0,0 +1,215 @@ + + +
+ 2012-04-05T15:00:11 + Detector + Unknown + /home/michael/Documents/School/EC311/lab6/iseconfig/Detector.xreport + /home/michael/Documents/School/EC311/lab6 + 2012-04-05T15:00:10 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/iseconfig/lab6.projectmgr b/iseconfig/lab6.projectmgr new file mode 100644 index 0000000..d839514 --- /dev/null +++ b/iseconfig/lab6.projectmgr @@ -0,0 +1,58 @@ + + + + + + + + + 2 + + + Unassigned User Library Modules + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000144000000020000000100000000000000000200000064ffffffff000000810000000300000002000001440000000100000003000000000000000100000003 + true + Unassigned User Library Modules + + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000154000000010000000100000000000000000000000064ffffffff000000810000000000000001000001540000000100000000 + false + + + + + 1 + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000157000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004a00000001000000000000002800000001000000000000007900000001000000000000006c0000000100000000 + false + + + + + 1 + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000117000000010001000100000000000000000000000064ffffffff000000810000000000000001000001170000000100000000 + false + work + + 000000ff00000000000000020000013f0000012001000000060100000002 + Implementation + diff --git a/isim.cmd b/isim.cmd new file mode 100644 index 0000000..fff18e8 --- /dev/null +++ b/isim.cmd @@ -0,0 +1,3 @@ +onerror {resume} +wave add / +run 1000 ns; diff --git a/isim.log b/isim.log new file mode 100644 index 0000000..4490dcf --- /dev/null +++ b/isim.log @@ -0,0 +1,37 @@ +ISim log file +Running: /home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.wdb +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +Time resolution is 1 ps +# onerror resume +# wave add / +# run 1000 ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. +ISim O.87xd (signature 0x8ddf5b5d) +WARNING: A WEBPACK license was found. +WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. +WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. +This is a Lite version of ISim. +# run 1000 ns +Simulator is doing circuit initialization process. +Finished circuit initialization process. diff --git a/isim/TEST_Detector_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg b/isim/TEST_Detector_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg new file mode 100644 index 0000000..c92f755 Binary files /dev/null and b/isim/TEST_Detector_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg differ diff --git a/isim/TEST_Detector_isim_beh.exe.sim/TEST_Detector_isim_beh.exe b/isim/TEST_Detector_isim_beh.exe.sim/TEST_Detector_isim_beh.exe new file mode 100755 index 0000000..d1311cc Binary files /dev/null and b/isim/TEST_Detector_isim_beh.exe.sim/TEST_Detector_isim_beh.exe differ diff --git a/isim/TEST_Detector_isim_beh.exe.sim/isimcrash.log b/isim/TEST_Detector_isim_beh.exe.sim/isimcrash.log new file mode 100644 index 0000000..e69de29 diff --git a/isim/TEST_Detector_isim_beh.exe.sim/isimkernel.log b/isim/TEST_Detector_isim_beh.exe.sim/isimkernel.log new file mode 100644 index 0000000..52d56ea --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/isimkernel.log @@ -0,0 +1,10 @@ +Command line: + TEST_Detector_isim_beh.exe + -simmode gui + -simrunnum 0 + -socket 42292 + +Thu Apr 5 15:29:09 2012 + + + Elaboration Time: 0.01 sec diff --git a/isim/TEST_Detector_isim_beh.exe.sim/netId.dat b/isim/TEST_Detector_isim_beh.exe.sim/netId.dat new file mode 100644 index 0000000..6f94b14 Binary files /dev/null and b/isim/TEST_Detector_isim_beh.exe.sim/netId.dat differ diff --git a/isim/TEST_Detector_isim_beh.exe.sim/tmp_save/_1 b/isim/TEST_Detector_isim_beh.exe.sim/tmp_save/_1 new file mode 100644 index 0000000..ce05ccc Binary files /dev/null and b/isim/TEST_Detector_isim_beh.exe.sim/tmp_save/_1 differ diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.c b/isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.c new file mode 100644 index 0000000..8e9fb43 --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.c @@ -0,0 +1,36 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +#include "xsi.h" + +struct XSI_INFO xsi_info; + + + +int main(int argc, char **argv) +{ + xsi_init_design(argc, argv); + xsi_register_info(&xsi_info); + + xsi_register_min_prec_unit(-12); + work_m_13872111861810629931_1087962131_init(); + work_m_14253225476704866645_1235880303_init(); + work_m_16541823861846354283_2073120511_init(); + + + xsi_register_tops("work_m_14253225476704866645_1235880303"); + xsi_register_tops("work_m_16541823861846354283_2073120511"); + + + return xsi_run_simulation(argc, argv); + +} diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.lin64.o b/isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.lin64.o new file mode 100644 index 0000000..7e43768 Binary files /dev/null and b/isim/TEST_Detector_isim_beh.exe.sim/work/TEST_Detector_isim_beh.exe_main.lin64.o differ diff --git a/isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.c b/isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.c new file mode 100644 index 0000000..47cffce --- /dev/null +++ b/isim/TEST_Detector_isim_beh.exe.sim/work/m_13872111861810629931_1087962131.c @@ -0,0 +1,547 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0x8ddf5b5d */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +static const char *ng0 = "/home/michael/Documents/School/EC311/lab6/Detector.v"; +static int ng1[] = {0, 0}; +static unsigned int ng2[] = {0U, 0U}; +static unsigned int ng3[] = {1U, 0U}; +static unsigned int ng4[] = {2U, 0U}; +static unsigned int ng5[] = {3U, 0U}; +static int ng6[] = {1, 0}; + + + +static void Initial_33_0(char *t0) +{ + char *t1; + char *t2; + +LAB0: xsi_set_current_line(33, ng0); + +LAB2: xsi_set_current_line(34, ng0); + t1 = ((char*)((ng1))); + t2 = (t0 + 1928); + xsi_vlogvar_assign_value(t2, t1, 0, 0, 2); + xsi_set_current_line(35, ng0); + t1 = ((char*)((ng1))); + t2 = (t0 + 1768); + xsi_vlogvar_assign_value(t2, t1, 0, 0, 1); + +LAB1: return; +} + +static void Always_38_1(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + unsigned int t6; + unsigned int t7; + unsigned int t8; + unsigned int t9; + unsigned int t10; + char *t11; + char *t12; + +LAB0: t1 = (t0 + 3248U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(38, ng0); + t2 = (t0 + 4064); + *((int *)t2) = 1; + t3 = (t0 + 3280); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(38, ng0); + +LAB5: xsi_set_current_line(39, ng0); + t4 = (t0 + 1368U); + t5 = *((char **)t4); + t4 = (t5 + 4); + t6 = *((unsigned int *)t4); + t7 = (~(t6)); + t8 = *((unsigned int *)t5); + t9 = (t8 & t7); + t10 = (t9 != 0); + if (t10 > 0) + goto LAB6; + +LAB7: xsi_set_current_line(41, ng0); + +LAB10: xsi_set_current_line(42, ng0); + t2 = (t0 + 2088); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t0 + 1928); + xsi_vlogvar_wait_assign_value(t5, t4, 0, 0, 2, 0LL); + +LAB8: goto LAB2; + +LAB6: xsi_set_current_line(39, ng0); + +LAB9: xsi_set_current_line(40, ng0); + t11 = ((char*)((ng1))); + t12 = (t0 + 1928); + xsi_vlogvar_wait_assign_value(t12, t11, 0, 0, 2, 0LL); + goto LAB8; + +} + +static void Always_46_2(char *t0) +{ + char t9[8]; + char t10[8]; + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + int t8; + char *t11; + char *t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + unsigned int t16; + unsigned int t17; + char *t18; + char *t19; + unsigned int t20; + unsigned int t21; + unsigned int t22; + char *t23; + unsigned int t24; + unsigned int t25; + unsigned int t26; + unsigned int t27; + char *t28; + char *t29; + +LAB0: t1 = (t0 + 3496U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(46, ng0); + t2 = (t0 + 4080); + *((int *)t2) = 1; + t3 = (t0 + 3528); + *((char **)t3) = t2; + *((char **)t1) = &&LAB4; + +LAB1: return; +LAB4: xsi_set_current_line(46, ng0); + +LAB5: xsi_set_current_line(47, ng0); + t4 = (t0 + 1928); + t5 = (t4 + 56U); + t6 = *((char **)t5); + +LAB6: t7 = ((char*)((ng2))); + t8 = xsi_vlog_unsigned_case_compare(t6, 2, t7, 2); + if (t8 == 1) + goto LAB7; + +LAB8: t2 = ((char*)((ng3))); + t8 = xsi_vlog_unsigned_case_compare(t6, 2, t2, 2); + if (t8 == 1) + goto LAB9; + +LAB10: t2 = ((char*)((ng4))); + t8 = xsi_vlog_unsigned_case_compare(t6, 2, t2, 2); + if (t8 == 1) + goto LAB11; + +LAB12: t2 = ((char*)((ng5))); + t8 = xsi_vlog_unsigned_case_compare(t6, 2, t2, 2); + if (t8 == 1) + goto LAB13; + +LAB14: +LAB16: +LAB15: xsi_set_current_line(52, ng0); + t2 = ((char*)((ng2))); + t3 = (t0 + 2088); + xsi_vlogvar_assign_value(t3, t2, 0, 0, 2); + +LAB17: goto LAB2; + +LAB7: xsi_set_current_line(48, ng0); + t11 = (t0 + 1048U); + t12 = *((char **)t11); + memset(t10, 0, 8); + t11 = (t12 + 4); + t13 = *((unsigned int *)t11); + t14 = (~(t13)); + t15 = *((unsigned int *)t12); + t16 = (t15 & t14); + t17 = (t16 & 1U); + if (t17 != 0) + goto LAB18; + +LAB19: if (*((unsigned int *)t11) != 0) + goto LAB20; + +LAB21: t19 = (t10 + 4); + t20 = *((unsigned int *)t10); + t21 = *((unsigned int *)t19); + t22 = (t20 || t21); + if (t22 > 0) + goto LAB22; + +LAB23: t24 = *((unsigned int *)t10); + t25 = (~(t24)); + t26 = *((unsigned int *)t19); + t27 = (t25 || t26); + if (t27 > 0) + goto LAB24; + +LAB25: if (*((unsigned int *)t19) > 0) + goto LAB26; + +LAB27: if (*((unsigned int *)t10) > 0) + goto LAB28; + +LAB29: memcpy(t9, t28, 8); + +LAB30: t29 = (t0 + 2088); + xsi_vlogvar_assign_value(t29, t9, 0, 0, 2); + goto LAB17; + +LAB9: xsi_set_current_line(49, ng0); + t3 = (t0 + 1048U); + t4 = *((char **)t3); + memset(t10, 0, 8); + t3 = (t4 + 4); + t13 = *((unsigned int *)t3); + t14 = (~(t13)); + t15 = *((unsigned int *)t4); + t16 = (t15 & t14); + t17 = (t16 & 1U); + if (t17 != 0) + goto LAB31; + +LAB32: if (*((unsigned int *)t3) != 0) + goto LAB33; + +LAB34: t7 = (t10 + 4); + t20 = *((unsigned int *)t10); + t21 = *((unsigned int *)t7); + t22 = (t20 || t21); + if (t22 > 0) + goto LAB35; + +LAB36: t24 = *((unsigned int *)t10); + t25 = (~(t24)); + t26 = *((unsigned int *)t7); + t27 = (t25 || t26); + if (t27 > 0) + goto LAB37; + +LAB38: if (*((unsigned int *)t7) > 0) + goto LAB39; + +LAB40: if (*((unsigned int *)t10) > 0) + goto LAB41; + +LAB42: memcpy(t9, t12, 8); + +LAB43: t18 = (t0 + 2088); + xsi_vlogvar_assign_value(t18, t9, 0, 0, 2); + goto LAB17; + +LAB11: xsi_set_current_line(50, ng0); + t3 = (t0 + 1048U); + t4 = *((char **)t3); + memset(t10, 0, 8); + t3 = (t4 + 4); + t13 = *((unsigned int *)t3); + t14 = (~(t13)); + t15 = *((unsigned int *)t4); + t16 = (t15 & t14); + t17 = (t16 & 1U); + if (t17 != 0) + goto LAB44; + +LAB45: if (*((unsigned int *)t3) != 0) + goto LAB46; + +LAB47: t7 = (t10 + 4); + t20 = *((unsigned int *)t10); + t21 = *((unsigned int *)t7); + t22 = (t20 || t21); + if (t22 > 0) + goto LAB48; + +LAB49: t24 = *((unsigned int *)t10); + t25 = (~(t24)); + t26 = *((unsigned int *)t7); + t27 = (t25 || t26); + if (t27 > 0) + goto LAB50; + +LAB51: if (*((unsigned int *)t7) > 0) + goto LAB52; + +LAB53: if (*((unsigned int *)t10) > 0) + goto LAB54; + +LAB55: memcpy(t9, t12, 8); + +LAB56: t18 = (t0 + 2088); + xsi_vlogvar_assign_value(t18, t9, 0, 0, 2); + goto LAB17; + +LAB13: xsi_set_current_line(51, ng0); + t3 = (t0 + 1048U); + t4 = *((char **)t3); + memset(t10, 0, 8); + t3 = (t4 + 4); + t13 = *((unsigned int *)t3); + t14 = (~(t13)); + t15 = *((unsigned int *)t4); + t16 = (t15 & t14); + t17 = (t16 & 1U); + if (t17 != 0) + goto LAB57; + +LAB58: if (*((unsigned int *)t3) != 0) + goto LAB59; + +LAB60: t7 = (t10 + 4); + t20 = *((unsigned int *