From c5c3101483a4c2facd67f514f0c320b4192f5844 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Thu, 5 Apr 2012 15:53:47 -0400
Subject: lab6

---
 DisplayController.v | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)
 create mode 100644 DisplayController.v

(limited to 'DisplayController.v')

diff --git a/DisplayController.v b/DisplayController.v
new file mode 100644
index 0000000..9e4cc66
--- /dev/null
+++ b/DisplayController.v
@@ -0,0 +1,48 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:03:47 03/16/2012 
+// Design Name: 
+// Module Name:    DisplayController 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module DisplayController(
+    input [3:0] A,
+    input [3:0] B,
+	 input clk_in,
+	 input rst,
+    output [6:0] result,
+    output [3:0] AN
+    );
+	 
+reg [3:0] AN;
+reg [6:0] result = 0;
+
+wire [6:0] ssd1;
+wire [6:0] ssd2;
+
+reg prev = 0;
+
+SevSegDisp d1(.A(A), .result(ssd1));
+SevSegDisp d2(.A(B), .result(ssd2));
+
+always @( posedge clk_in ) begin
+	prev <= ~prev;
+	result <= prev ? ssd1 : ssd2;
+	AN <= { ~prev, 2'b11, prev };
+end
+
+
+endmodule
-- 
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