Running: /home/michael/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab6/TEST_Detector_beh.prj" "work.TEST_Detector" "work.glbl" 
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 2
Turning on mult-threading, number of parallel sub-compilation jobs: 4 
Determining compilation order of HDL files
Analyzing Verilog file "/home/michael/Documents/School/EC311/lab6/Detector.v" into library work
WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab6/Detector.v" Line 29: Redeclaration of ansi port state is not allowed
WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab6/Detector.v" Line 31: Redeclaration of ansi port result is not allowed
Analyzing Verilog file "/home/michael/Documents/School/EC311/lab6/TEST_Detector.v" into library work
Analyzing Verilog file "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 94996 KB
Fuse CPU Usage: 1550 ms
Compiling module Detector
Compiling module TEST_Detector
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 3 Verilog Units
Built simulation executable /home/michael/Documents/School/EC311/lab6/TEST_Detector_isim_beh.exe
Fuse Memory Usage: 393016 KB
Fuse CPU Usage: 1580 ms
GCC CPU Usage: 380 ms