From a93f8d8f6331f28b8862258db95cea3ac14f7787 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Sun, 2 Dec 2012 12:11:54 -0500
Subject: add verilog code

---
 adder_16bit.v          | 36 +++++++++++++++++++
 adder_32bit.v          | 34 ++++++++++++++++++
 adder_4bit.v           | 37 +++++++++++++++++++
 adder_64bit.v          | 34 ++++++++++++++++++
 adder_64bit_csel.v     | 41 +++++++++++++++++++++
 adder_64bit_csel4way.v | 56 +++++++++++++++++++++++++++++
 csel.v                 | 31 ++++++++++++++++
 full_adder.v           | 96 ++++++++++++++++++++++++++++++++++++++++++++++++++
 mux2_16bit.v           | 33 +++++++++++++++++
 mux2_1bit.v            | 37 +++++++++++++++++++
 mux2_32bit.v           | 31 ++++++++++++++++
 mux2_4bit.v            | 33 +++++++++++++++++
 12 files changed, 499 insertions(+)
 create mode 100755 adder_16bit.v
 create mode 100755 adder_32bit.v
 create mode 100755 adder_4bit.v
 create mode 100755 adder_64bit.v
 create mode 100755 adder_64bit_csel.v
 create mode 100755 adder_64bit_csel4way.v
 create mode 100755 csel.v
 create mode 100755 full_adder.v
 create mode 100755 mux2_16bit.v
 create mode 100755 mux2_1bit.v
 create mode 100755 mux2_32bit.v
 create mode 100755 mux2_4bit.v

diff --git a/adder_16bit.v b/adder_16bit.v
new file mode 100755
index 0000000..c805b4f
--- /dev/null
+++ b/adder_16bit.v
@@ -0,0 +1,36 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:34:30 09/26/2012 
+// Design Name: 
+// Module Name:    adder_16bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies:
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module adder_16bit(
+    input [15:0] A,
+    input [15:0] B,
+    input Carry_In,
+    output [15:0] Sum,
+    output Carry_Out
+    );
+
+wire c1, c2, c3;
+
+adder_4bit a0(.Carry_Out(c1), .Sum(Sum[3:0]), .A(A[3:0]), .B(B[3:0]), .Carry_In(Carry_In));
+adder_4bit a1(.Carry_Out(c2), .Sum(Sum[7:4]), .A(A[7:4]), .B(B[7:4]), .Carry_In(c1));
+adder_4bit a2(.Carry_Out(c3), .Sum(Sum[11:8]), .A(A[11:8]), .B(B[11:8]), .Carry_In(c2));
+adder_4bit a3(.Carry_Out(Carry_Out), .Sum(Sum[15:12]), .A(A[15:12]), .B(B[15:12]), .Carry_In(c3));
+
+endmodule
diff --git a/adder_32bit.v b/adder_32bit.v
new file mode 100755
index 0000000..544381d
--- /dev/null
+++ b/adder_32bit.v
@@ -0,0 +1,34 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:41:53 09/26/2012 
+// Design Name: 
+// Module Name:    adder_32bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module adder_32bit(
+    input [31:0] A,
+    input [31:0] B,
+    input Carry_In,
+    output [31:0] Sum,
+    output Carry_Out
+    );
+
+wire c1;
+
+adder_16bit a0(.Carry_Out(c1), .Sum(Sum[15:0]), .A(A[15:0]), .B(B[15:0]), .Carry_In(Carry_In));
+adder_16bit a1(.Carry_Out(Carry_Out), .Sum(Sum[31:16]), .A(A[31:16]), .B(B[31:16]), .Carry_In(c1));
+
+endmodule
diff --git a/adder_4bit.v b/adder_4bit.v
new file mode 100755
index 0000000..2e48c61
--- /dev/null
+++ b/adder_4bit.v
@@ -0,0 +1,37 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:05:10 09/26/2012 
+// Design Name: 
+// Module Name:    adder_4bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module adder_4bit(
+    input [3:0] A,
+    input [3:0] B,
+    input Carry_In,
+    output [3:0] Sum,
+    output Carry_Out
+    );
+
+wire c1, c2, c3; // intermediate carry wires
+
+// 4-bit ripple carry adder
+fa fa0(.Carry_Out(c1), .Sum(Sum[0]), .A(A[0]), .B(B[0]), .Carry_In(Carry_In) );
+fa fa1(.Carry_Out(c2), .Sum(Sum[1]), .A(A[1]), .B(B[1]), .Carry_In(c1));
+fa fa2(.Carry_Out(c3), .Sum(Sum[2]), .A(A[2]), .B(B[2]), .Carry_In(c2));
+fa fa3(.Carry_Out(Carry_Out), .Sum(Sum[3]), .A(A[3]), .B(B[3]), .Carry_In(c3));
+
+endmodule
diff --git a/adder_64bit.v b/adder_64bit.v
new file mode 100755
index 0000000..05b7934
--- /dev/null
+++ b/adder_64bit.v
@@ -0,0 +1,34 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:10:03 09/26/2012 
+// Design Name: 
+// Module Name:    adder_64bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module adder_64bit(
+    input [63:0] A,
+    input [63:0] B,
+    input Carry_In,
+    output [63:0] Sum,
+    output Carry_Out
+    );
+	 
+wire c1;
+
+adder_32bit a1(.Carry_Out(c1), .Sum(Sum[31:0]), .A(A[31:0]), .B(B[31:0]), .Carry_In(Carry_In));
+adder_32bit a2(.Carry_Out(Carry_Out), .Sum(Sum[63:32]), .A(A[63:32]), .B(B[63:32]), .Carry_In(c1));
+
+endmodule
diff --git a/adder_64bit_csel.v b/adder_64bit_csel.v
new file mode 100755
index 0000000..4c7ebb7
--- /dev/null
+++ b/adder_64bit_csel.v
@@ -0,0 +1,41 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:50:17 09/26/2012 
+// Design Name: 
+// Module Name:    adder_64bit_csel 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module adder_64bit_csel(
+    input [63:0] A,
+    input [63:0] B,
+    input Carry_In,
+    output [63:0] Sum,
+    output Carry_Out
+    );
+	 
+wire c1, c2, c3;
+
+wire [31:0] o1, o2; // possible outputs for higher bits
+
+adder_32bit a1(.Carry_Out(c1), .Sum(Sum[31:0]), .A(A[31:0]), .B(B[31:0]), .Carry_In(Carry_In));
+
+adder_32bit a2(.Carry_Out(c2), .Sum(o1), .A(A[63:32]), .B(B[63:32]), .Carry_In(1'b0));
+adder_32bit a3(.Carry_Out(c3), .Sum(o2), .A(A[63:32]), .B(B[63:32]), .Carry_In(1'b1));
+
+mux2_32bit m1(.a(o2), .b(o1), .sel(c1), .o(Sum[63:32]));
+mux2_1bit m2(.a(c3), .b(c2), .sel(c1), .o(Carry_Out));
+
+endmodule
diff --git a/adder_64bit_csel4way.v b/adder_64bit_csel4way.v
new file mode 100755
index 0000000..45c1b53
--- /dev/null
+++ b/adder_64bit_csel4way.v
@@ -0,0 +1,56 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    13:29:27 09/27/2012 
+// Design Name: 
+// Module Name:    adder_64bit_csel4 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module adder_64bit_csel4(
+    input [63:0] A,
+    input [63:0] B,
+    input Carry_In,
+    output [63:0] Sum,
+    output Carry_Out
+    );
+
+wire c0, c10, c11, c20, c21, c30, c31; // possible carry terms
+
+wire [15:0] s10, s11, s20, s21, s30, s31; // sum terms
+
+wire p1, p2;
+
+adder_16bit a00(.Carry_Out(c0), .Sum(Sum[15:0]), .A(A[15:0]), .B(B[15:0]), .Carry_In(Carry_In));
+
+
+adder_16bit a10(.Carry_Out(c10), .Sum(s10), .A(A[31:16]), .B(B[31:16]), .Carry_In(1'b0));
+adder_16bit a11(.Carry_Out(c11), .Sum(s11), .A(A[31:16]), .B(B[31:16]), .Carry_In(1'b1));
+
+mux2_16bit m1(.a(s11), .b(s10), .sel(c0), .o(Sum[31:16]));
+
+adder_16bit a20(.Carry_Out(c20), .Sum(s20), .A(A[47:32]), .B(B[47:32]), .Carry_In(1'b0));
+adder_16bit a21(.Carry_Out(c21), .Sum(s21), .A(A[47:32]), .B(B[47:32]), .Carry_In(1'b1));
+
+csel cs1(.c_prev(c0), .c0(c20), .c1(c21), .sel(p1));
+mux2_16bit m2(.a(s21), .b(s20), .sel(p1), .o(Sum[47:32]));
+
+adder_16bit a30(.Carry_Out(c30), .Sum(s30), .A(A[63:48]), .B(B[63:48]), .Carry_In(1'b0));
+adder_16bit a31(.Carry_Out(c31), .Sum(s31), .A(A[63:48]), .B(B[63:48]), .Carry_In(1'b1));
+
+csel cs2(.c_prev(p1), .c0(c30), .c1(c31), .sel(p2));
+mux2_16bit m3(.a(s31), .b(s30), .sel(p2), .o(Sum[63:48]));
+mux2_1bit m4(.a(c31), .b(c30), .sel(p2), .o(Carry_Out));
+
+endmodule
diff --git a/csel.v b/csel.v
new file mode 100755
index 0000000..d1b29d7
--- /dev/null
+++ b/csel.v
@@ -0,0 +1,31 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    20:27:50 09/27/2012 
+// Design Name: 
+// Module Name:    csel 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module csel(
+    input c_prev,
+    input c0,
+    input c1,
+    output sel
+    );
+wire i1;
+
+and #1 a1(i1, c_prev, c1);
+or #1 o1(sel, c0, i1);
+endmodule
diff --git a/full_adder.v b/full_adder.v
new file mode 100755
index 0000000..85ec9db
--- /dev/null
+++ b/full_adder.v
@@ -0,0 +1,96 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    14:19:23 09/26/2012 
+// Design Name: 
+// Module Name:    full_adder 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+/////////////////////////////////////////////////////////////////////////////////
+
+
+
+module fa(
+    input A,
+    input B,
+    input Carry_In,
+    output Sum,
+    output Carry_Out
+    );
+`define timed
+`ifdef timed
+
+wire s1, s2, s3, s4; // sum wires
+wire c1, c2, c3; // carry wires
+wire ia, ib, ic; // inverted wires
+
+// invert wires ad needed for the sum
+not n1(ia, A);
+not n2(ib, B);
+not n3(ic, Carry_In);
+
+// SUM CALCULATION
+
+// compute relevant minterms
+and #1 a1(s1, ia, ib, Carry_In);
+and #1 a2(s2, ia, B, ic);
+and #1 a3(s3, A, ib, ic);
+and #1 a4(s4, A, B, Carry_In);
+
+// or minterm results
+or #1 sum(Sum, s1, s2, s3, s4);
+
+// CARRY CALCULATION
+
+// compute minterms
+and #1 ca1(c1, A, B);
+and #1 ca2(c2, A, Carry_In);
+and #1 ca3(c3, B, Carry_In);
+
+// or results
+or #1 cout(Carry_Out, c1, c2, c3);
+
+
+`else
+wire s1, s2, s3, s4; // sum wires
+wire c1, c2, c3; // carry wires
+wire ia, ib, ic; // inverted wires
+
+// invert wires ad needed for the sum
+not n1(ia, A);
+not n2(ib, B);
+not n3(ic, Carry_In);
+
+// SUM CALCULATION
+
+// compute relevant minterms
+and a1(s1, ia, ib, Carry_In);
+and a2(s2, ia, B, ic);
+and a3(s3, A, ib, ic);
+and a4(s4, A, B, Carry_In);
+
+// or minterm results
+or sum(Sum, s1, s2, s3, s4);
+
+// CARRY CALCULATION
+
+// compute minterms
+and ca1(c1, A, B);
+and ca2(c2, A, Carry_In);
+and ca3(c3, B, Carry_In);
+
+// or results
+or cout(Carry_Out, c1, c2, c3); 
+`endif
+endmodule
diff --git a/mux2_16bit.v b/mux2_16bit.v
new file mode 100755
index 0000000..0192f8b
--- /dev/null
+++ b/mux2_16bit.v
@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:41:28 09/27/2012 
+// Design Name: 
+// Module Name:    mux2_16bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux2_16bit(
+    input [15:0] a,
+    input [15:0] b,
+    input sel,
+    output [15:0] o
+    );
+
+mux2_4bit m0(.a(a[3:0]), .b(b[3:0]), .sel(sel), .o(o[3:0]));
+mux2_4bit m1(.a(a[7:4]), .b(b[7:4]), .sel(sel), .o(o[7:4]));
+mux2_4bit m2(.a(a[11:8]), .b(b[11:8]), .sel(sel), .o(o[11:8]));
+mux2_4bit m3(.a(a[15:12]), .b(b[15:12]), .sel(sel), .o(o[15:12]));
+
+endmodule
diff --git a/mux2_1bit.v b/mux2_1bit.v
new file mode 100755
index 0000000..3a5e225
--- /dev/null
+++ b/mux2_1bit.v
@@ -0,0 +1,37 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:34:03 09/27/2012 
+// Design Name: 
+// Module Name:    mux2_1bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux2_1bit(
+    input a,
+    input b,
+    input sel,
+    output o
+    );
+
+wire i1; // inverted sel
+wire a1, a2; // ands
+not n1(i1, sel);
+
+and and1(a1, a, sel);
+and and2(a2, b, i1);
+
+or or1(o, a1, a2);
+
+endmodule
diff --git a/mux2_32bit.v b/mux2_32bit.v
new file mode 100755
index 0000000..5cf2d44
--- /dev/null
+++ b/mux2_32bit.v
@@ -0,0 +1,31 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:57:54 09/27/2012 
+// Design Name: 
+// Module Name:    mux2_32bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux2_32bit(
+    input [31:0] a,
+    input [31:0] b,
+    input sel,
+    output [31:0] o
+    );
+
+mux2_16bit m1(.a(a[15:0]), .b(b[15:0]), .sel(sel), .o(o[15:0]));
+mux2_16bit m2(.a(a[31:16]), .b(b[31:16]), .sel(sel), .o(o[31:16]));
+
+endmodule
diff --git a/mux2_4bit.v b/mux2_4bit.v
new file mode 100755
index 0000000..5dd6dc7
--- /dev/null
+++ b/mux2_4bit.v
@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    11:37:54 09/27/2012 
+// Design Name: 
+// Module Name:    mux2_4bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux2_4bit(
+    input [3:0] a,
+    input [3:0] b,
+    input sel,
+    input [3:0] o
+    );
+
+mux2_1bit m0(.a(a[0]), .b(b[0]), .sel(sel), .o(o[0]));
+mux2_1bit m1(.a(a[1]), .b(b[1]), .sel(sel), .o(o[1]));
+mux2_1bit m2(.a(a[2]), .b(b[2]), .sel(sel), .o(o[2]));
+mux2_1bit m3(.a(a[3]), .b(b[3]), .sel(sel), .o(o[3]));
+
+endmodule
-- 
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