From a93f8d8f6331f28b8862258db95cea3ac14f7787 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Sun, 2 Dec 2012 12:11:54 -0500
Subject: add verilog code

---
 adder_32bit.v | 34 ++++++++++++++++++++++++++++++++++
 1 file changed, 34 insertions(+)
 create mode 100755 adder_32bit.v

(limited to 'adder_32bit.v')

diff --git a/adder_32bit.v b/adder_32bit.v
new file mode 100755
index 0000000..544381d
--- /dev/null
+++ b/adder_32bit.v
@@ -0,0 +1,34 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:41:53 09/26/2012 
+// Design Name: 
+// Module Name:    adder_32bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module adder_32bit(
+    input [31:0] A,
+    input [31:0] B,
+    input Carry_In,
+    output [31:0] Sum,
+    output Carry_Out
+    );
+
+wire c1;
+
+adder_16bit a0(.Carry_Out(c1), .Sum(Sum[15:0]), .A(A[15:0]), .B(B[15:0]), .Carry_In(Carry_In));
+adder_16bit a1(.Carry_Out(Carry_Out), .Sum(Sum[31:16]), .A(A[31:16]), .B(B[31:16]), .Carry_In(c1));
+
+endmodule
-- 
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