From a93f8d8f6331f28b8862258db95cea3ac14f7787 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Sun, 2 Dec 2012 12:11:54 -0500
Subject: add verilog code

---
 adder_4bit.v | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100755 adder_4bit.v

(limited to 'adder_4bit.v')

diff --git a/adder_4bit.v b/adder_4bit.v
new file mode 100755
index 0000000..2e48c61
--- /dev/null
+++ b/adder_4bit.v
@@ -0,0 +1,37 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    15:05:10 09/26/2012 
+// Design Name: 
+// Module Name:    adder_4bit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module adder_4bit(
+    input [3:0] A,
+    input [3:0] B,
+    input Carry_In,
+    output [3:0] Sum,
+    output Carry_Out
+    );
+
+wire c1, c2, c3; // intermediate carry wires
+
+// 4-bit ripple carry adder
+fa fa0(.Carry_Out(c1), .Sum(Sum[0]), .A(A[0]), .B(B[0]), .Carry_In(Carry_In) );
+fa fa1(.Carry_Out(c2), .Sum(Sum[1]), .A(A[1]), .B(B[1]), .Carry_In(c1));
+fa fa2(.Carry_Out(c3), .Sum(Sum[2]), .A(A[2]), .B(B[2]), .Carry_In(c2));
+fa fa3(.Carry_Out(Carry_Out), .Sum(Sum[3]), .A(A[3]), .B(B[3]), .Carry_In(c3));
+
+endmodule
-- 
cgit v1.2.3