From a93f8d8f6331f28b8862258db95cea3ac14f7787 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Sun, 2 Dec 2012 12:11:54 -0500
Subject: add verilog code

---
 adder_64bit_csel.v | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100755 adder_64bit_csel.v

(limited to 'adder_64bit_csel.v')

diff --git a/adder_64bit_csel.v b/adder_64bit_csel.v
new file mode 100755
index 0000000..4c7ebb7
--- /dev/null
+++ b/adder_64bit_csel.v
@@ -0,0 +1,41 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    16:50:17 09/26/2012 
+// Design Name: 
+// Module Name:    adder_64bit_csel 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module adder_64bit_csel(
+    input [63:0] A,
+    input [63:0] B,
+    input Carry_In,
+    output [63:0] Sum,
+    output Carry_Out
+    );
+	 
+wire c1, c2, c3;
+
+wire [31:0] o1, o2; // possible outputs for higher bits
+
+adder_32bit a1(.Carry_Out(c1), .Sum(Sum[31:0]), .A(A[31:0]), .B(B[31:0]), .Carry_In(Carry_In));
+
+adder_32bit a2(.Carry_Out(c2), .Sum(o1), .A(A[63:32]), .B(B[63:32]), .Carry_In(1'b0));
+adder_32bit a3(.Carry_Out(c3), .Sum(o2), .A(A[63:32]), .B(B[63:32]), .Carry_In(1'b1));
+
+mux2_32bit m1(.a(o2), .b(o1), .sel(c1), .o(Sum[63:32]));
+mux2_1bit m2(.a(c3), .b(c2), .sel(c1), .o(Carry_Out));
+
+endmodule
-- 
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