From a93f8d8f6331f28b8862258db95cea3ac14f7787 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Sun, 2 Dec 2012 12:11:54 -0500 Subject: add verilog code --- adder_64bit_csel4way.v | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100755 adder_64bit_csel4way.v (limited to 'adder_64bit_csel4way.v') diff --git a/adder_64bit_csel4way.v b/adder_64bit_csel4way.v new file mode 100755 index 0000000..45c1b53 --- /dev/null +++ b/adder_64bit_csel4way.v @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:29:27 09/27/2012 +// Design Name: +// Module Name: adder_64bit_csel4 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module adder_64bit_csel4( + input [63:0] A, + input [63:0] B, + input Carry_In, + output [63:0] Sum, + output Carry_Out + ); + +wire c0, c10, c11, c20, c21, c30, c31; // possible carry terms + +wire [15:0] s10, s11, s20, s21, s30, s31; // sum terms + +wire p1, p2; + +adder_16bit a00(.Carry_Out(c0), .Sum(Sum[15:0]), .A(A[15:0]), .B(B[15:0]), .Carry_In(Carry_In)); + + +adder_16bit a10(.Carry_Out(c10), .Sum(s10), .A(A[31:16]), .B(B[31:16]), .Carry_In(1'b0)); +adder_16bit a11(.Carry_Out(c11), .Sum(s11), .A(A[31:16]), .B(B[31:16]), .Carry_In(1'b1)); + +mux2_16bit m1(.a(s11), .b(s10), .sel(c0), .o(Sum[31:16])); + +adder_16bit a20(.Carry_Out(c20), .Sum(s20), .A(A[47:32]), .B(B[47:32]), .Carry_In(1'b0)); +adder_16bit a21(.Carry_Out(c21), .Sum(s21), .A(A[47:32]), .B(B[47:32]), .Carry_In(1'b1)); + +csel cs1(.c_prev(c0), .c0(c20), .c1(c21), .sel(p1)); +mux2_16bit m2(.a(s21), .b(s20), .sel(p1), .o(Sum[47:32])); + +adder_16bit a30(.Carry_Out(c30), .Sum(s30), .A(A[63:48]), .B(B[63:48]), .Carry_In(1'b0)); +adder_16bit a31(.Carry_Out(c31), .Sum(s31), .A(A[63:48]), .B(B[63:48]), .Carry_In(1'b1)); + +csel cs2(.c_prev(p1), .c0(c30), .c1(c31), .sel(p2)); +mux2_16bit m3(.a(s31), .b(s30), .sel(p2), .o(Sum[63:48])); +mux2_1bit m4(.a(c31), .b(c30), .sel(p2), .o(Carry_Out)); + +endmodule -- cgit v1.2.3