From a93f8d8f6331f28b8862258db95cea3ac14f7787 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Sun, 2 Dec 2012 12:11:54 -0500 Subject: add verilog code --- csel.v | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100755 csel.v (limited to 'csel.v') diff --git a/csel.v b/csel.v new file mode 100755 index 0000000..d1b29d7 --- /dev/null +++ b/csel.v @@ -0,0 +1,31 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 20:27:50 09/27/2012 +// Design Name: +// Module Name: csel +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module csel( + input c_prev, + input c0, + input c1, + output sel + ); +wire i1; + +and #1 a1(i1, c_prev, c1); +or #1 o1(sel, c0, i1); +endmodule -- cgit v1.2.3