`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    16:50:17 09/26/2012 
// Design Name: 
// Module Name:    adder_64bit_csel 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module adder_64bit_csel(
    input [63:0] A,
    input [63:0] B,
    input Carry_In,
    output [63:0] Sum,
    output Carry_Out
    );
	 
wire c1, c2, c3;

wire [31:0] o1, o2; // possible outputs for higher bits

adder_32bit a1(.Carry_Out(c1), .Sum(Sum[31:0]), .A(A[31:0]), .B(B[31:0]), .Carry_In(Carry_In));

adder_32bit a2(.Carry_Out(c2), .Sum(o1), .A(A[63:32]), .B(B[63:32]), .Carry_In(1'b0));
adder_32bit a3(.Carry_Out(c3), .Sum(o2), .A(A[63:32]), .B(B[63:32]), .Carry_In(1'b1));

mux2_32bit m1(.a(o2), .b(o1), .sel(c1), .o(Sum[63:32]));
mux2_1bit m2(.a(c3), .b(c2), .sel(c1), .o(Carry_Out));

endmodule