`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:41:28 09/27/2012 
// Design Name: 
// Module Name:    mux2_16bit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mux2_16bit(
    input [15:0] a,
    input [15:0] b,
    input sel,
    output [15:0] o
    );

mux2_4bit m0(.a(a[3:0]), .b(b[3:0]), .sel(sel), .o(o[3:0]));
mux2_4bit m1(.a(a[7:4]), .b(b[7:4]), .sel(sel), .o(o[7:4]));
mux2_4bit m2(.a(a[11:8]), .b(b[11:8]), .sel(sel), .o(o[11:8]));
mux2_4bit m3(.a(a[15:12]), .b(b[15:12]), .sel(sel), .o(o[15:12]));

endmodule