From e64c18d0e30c33fe4609c881620fa937da7b8ce3 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Sun, 2 Dec 2012 12:13:10 -0500 Subject: make git repo --- verilog/DFF.v | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100755 verilog/DFF.v (limited to 'verilog/DFF.v') diff --git a/verilog/DFF.v b/verilog/DFF.v new file mode 100755 index 0000000..53ae504 --- /dev/null +++ b/verilog/DFF.v @@ -0,0 +1,27 @@ +//D Flip-flop +module DFF(D, // DFF Input + Q, // DFF Output + Write, // Only accept input when this is set + Reset, // Synchronous Reset + Clk); // Clock + + //-------------Input Ports----------------------------- + input D; + input Write; + input Reset; + input Clk; + //-------------Output Ports---------------------------- + output Q; + //-------------Wires----------------------------------- + //-------------Other----------------------------------- + reg data; + //------------Code Starts Here------------------------- + assign Q= data; + always @ (posedge Clk) + if (Reset) begin + data <= 1'b0; + end else begin + if(Write) + data <= D; + end +endmodule -- cgit v1.2.3