From e64c18d0e30c33fe4609c881620fa937da7b8ce3 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Sun, 2 Dec 2012 12:13:10 -0500
Subject: make git repo

---
 verilog/S3.v | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100755 verilog/S3.v

(limited to 'verilog/S3.v')

diff --git a/verilog/S3.v b/verilog/S3.v
new file mode 100755
index 0000000..2fa74ef
--- /dev/null
+++ b/verilog/S3.v
@@ -0,0 +1,53 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    02:50:52 10/22/2012 
+// Design Name: 
+// Module Name:    Stage3 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module Stage3(
+	alu_in,
+	wsel_in,
+	alu_out,
+	wsel_out,
+	clk,
+	reset
+    );
+parameter BITS=32;
+parameter RSELW=5;
+input clk, reset;
+input [BITS-1:0] alu_in;
+input [RSELW-1:0] wsel_in;
+
+output [BITS-1:0] alu_out;
+output [RSELW-1:0] wsel_out;
+
+nbit_reg #(BITS) rreg(
+	.nD(alu_in),
+	.nQ(alu_out),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+
+nbit_reg #(RSELW) wreg(
+	.nD(wsel_in),
+	.nQ(wsel_out),
+	.Write(1'b1),
+	.Clk(clk),
+	.Reset(reset)
+);
+endmodule
-- 
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