From e64c18d0e30c33fe4609c881620fa937da7b8ce3 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Sun, 2 Dec 2012 12:13:10 -0500
Subject: make git repo

---
 verilog/instruction_decode.v | 41 +++++++++++++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100755 verilog/instruction_decode.v

(limited to 'verilog/instruction_decode.v')

diff --git a/verilog/instruction_decode.v b/verilog/instruction_decode.v
new file mode 100755
index 0000000..f74e466
--- /dev/null
+++ b/verilog/instruction_decode.v
@@ -0,0 +1,41 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    20:27:39 10/21/2012 
+// Design Name: 
+// Module Name:    instruction_decode 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module instruction_decode(
+    output op_type,
+    output math_type,
+    output [2:0] alu_op,
+    output [4:0] r1sel,
+    output [4:0] r2sel,
+    output [4:0] r3sel,
+    output [15:0] immediate,
+    input [31:0] instruction
+);
+
+
+assign math_type = instruction[30];
+assign op_type = instruction[29];
+assign alu_op = instruction[28:26];
+assign r1sel = instruction[25:21];
+assign r2sel = instruction[20:16];
+assign r3sel = instruction[15:11];
+assign immediate = instruction[15:0];
+
+endmodule
-- 
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