From e64c18d0e30c33fe4609c881620fa937da7b8ce3 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Sun, 2 Dec 2012 12:13:10 -0500 Subject: make git repo --- verilog/mux_2to1.v | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100755 verilog/mux_2to1.v (limited to 'verilog/mux_2to1.v') diff --git a/verilog/mux_2to1.v b/verilog/mux_2to1.v new file mode 100755 index 0000000..48ad684 --- /dev/null +++ b/verilog/mux_2to1.v @@ -0,0 +1,34 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 13:02:11 10/05/2012 +// Design Name: +// Module Name: mux_2to1 +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module mux_2to1( + output out, + input sel, + input o0, + input o1 + ); + +wire a1, a2, n; +not n1(n, sel); +and ag1(a1, o0, n); +and ag2(a2, o1, sel); +or og1(out, a1, a2); + +endmodule -- cgit v1.2.3