From e64c18d0e30c33fe4609c881620fa937da7b8ce3 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Sun, 2 Dec 2012 12:13:10 -0500
Subject: make git repo

---
 verilog/mux_2to1_nbit.v | 39 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)
 create mode 100755 verilog/mux_2to1_nbit.v

(limited to 'verilog/mux_2to1_nbit.v')

diff --git a/verilog/mux_2to1_nbit.v b/verilog/mux_2to1_nbit.v
new file mode 100755
index 0000000..3e70955
--- /dev/null
+++ b/verilog/mux_2to1_nbit.v
@@ -0,0 +1,39 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    13:03:36 10/05/2012 
+// Design Name: 
+// Module Name:    mux_2to1_nbit 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mux_2to1_nbit(
+     out,
+     sel,
+     o0,
+     o1
+    );
+parameter BITS = 32;
+input [BITS-1:0] o1, o0;
+output [BITS-1:0] out;
+input sel;
+
+generate
+genvar i;
+	for (i = 0; i < BITS; i = i + 1) begin:muxgen
+		mux_2to1 m(out[i], sel, o0[i], o1[i]);
+	end
+endgenerate
+
+endmodule
-- 
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