From e64c18d0e30c33fe4609c881620fa937da7b8ce3 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Sun, 2 Dec 2012 12:13:10 -0500
Subject: make git repo

---
 verilog/nbit_demux.v | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100755 verilog/nbit_demux.v

(limited to 'verilog/nbit_demux.v')

diff --git a/verilog/nbit_demux.v b/verilog/nbit_demux.v
new file mode 100755
index 0000000..5be44c8
--- /dev/null
+++ b/verilog/nbit_demux.v
@@ -0,0 +1,33 @@
+//n bit DeMux
+// Specify the number of select lines as a parameter.
+module nbit_demux(DeMuxIn,   // DeMux input: 1 bit.
+                  DeMuxOut,  // DeMux output: 2^SELECT_WIDTH bits.
+						DeMuxSel); // DeMux select lines: SELECT_WIDTH bits.
+
+// Specifies the select line width.
+parameter SELECT_WIDTH = 3;
+
+//-------------Input Ports-----------------------------
+input  DeMuxIn;
+input  [SELECT_WIDTH-1:0] DeMuxSel;
+//-------------Output Ports----------------------------
+output [2 ** SELECT_WIDTH-1:0] DeMuxOut;
+//-------------Wires-----------------------------------
+wire [2 ** SELECT_WIDTH-1:0] select;
+//-------------Other-----------------------------------
+//------------Code Starts Here-------------------------
+
+generate
+	genvar i; // Instance variable
+	
+	// address decoder
+	assign select[2 ** SELECT_WIDTH-1:0] = 2 ** DeMuxSel[SELECT_WIDTH-1:0];
+	
+	// Generation for loop
+	for(i= 0;i< 2 ** SELECT_WIDTH;i= i+1)
+	begin:demux_loop
+		assign DeMuxOut[i] = DeMuxIn & select[i];
+	end	
+endgenerate
+
+endmodule
-- 
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