From e64c18d0e30c33fe4609c881620fa937da7b8ce3 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Sun, 2 Dec 2012 12:13:10 -0500
Subject: make git repo

---
 verilog/nbit_mux.v | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100755 verilog/nbit_mux.v

(limited to 'verilog/nbit_mux.v')

diff --git a/verilog/nbit_mux.v b/verilog/nbit_mux.v
new file mode 100755
index 0000000..fb5cd14
--- /dev/null
+++ b/verilog/nbit_mux.v
@@ -0,0 +1,19 @@
+//n bit Mux
+// Specify the number of select lines as a parameter.
+module nbit_mux(MuxIn,   // Mux input: 2^SELECT_WIDTH bits.
+                MuxOut,  // Mux output: 1 bit.
+					 MuxSel); // Mux select lines: SELECT_WIDTH bits.
+
+// Specifies the select line width.
+parameter SELECT_WIDTH = 3;
+
+//-------------Input Ports-----------------------------
+input  [2 ** SELECT_WIDTH-1:0] MuxIn;
+input  [SELECT_WIDTH-1:0] MuxSel;
+//-------------Output Ports----------------------------
+output MuxOut;
+//-------------Wires-----------------------------------
+//-------------Other-----------------------------------
+//------------Code Starts Here-------------------------
+assign MuxOut = MuxIn[MuxSel];
+endmodule
-- 
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