From e64c18d0e30c33fe4609c881620fa937da7b8ce3 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Sun, 2 Dec 2012 12:13:10 -0500
Subject: make git repo

---
 verilog/nbit_register_file.v | 76 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100755 verilog/nbit_register_file.v

(limited to 'verilog/nbit_register_file.v')

diff --git a/verilog/nbit_register_file.v b/verilog/nbit_register_file.v
new file mode 100755
index 0000000..8711209
--- /dev/null
+++ b/verilog/nbit_register_file.v
@@ -0,0 +1,76 @@
+// nbit_register_file
+//
+// A generic register file which can be parameterized
+// by the following:
+//
+// - number of register select lines REG_SELECT_WIDTH: 
+//   number of registers in the file is 2 to the power 
+//   of this number.
+//
+// - number of register bits DATA_WIDTH.
+//
+// Updates:
+// 10/18: Reset fix.
+// 10/21: Timing fix.
+//
+module nbit_register_file(WriteData,   // Input data
+                          ReadData1,   // Output data 1
+                          ReadData2,   // Output data 2
+                          ReadSelect1, // Select lines for output 1
+                          ReadSelect2, // Select lines for output 2
+                          WriteSelect, // Select lines for input
+                          WriteEnable, // Causes write to take place on posedge
+                          Reset,       // Synchronous reset
+                          Clk);        // Clock
+
+// Register select line size (number of registers is 2 
+// to the power of this number).
+parameter REG_SELECT_WIDTH = 1;
+// Register size in bits.
+parameter DATA_WIDTH = 32;
+
+//-------------Input Ports-----------------------------
+input [DATA_WIDTH-1:0]       WriteData;
+input [REG_SELECT_WIDTH-1:0] ReadSelect1;
+input [REG_SELECT_WIDTH-1:0] ReadSelect2;
+input [REG_SELECT_WIDTH-1:0] WriteSelect;
+input WriteEnable;
+input Reset;
+input Clk;
+//-------------Output Ports----------------------------
+output [DATA_WIDTH-1:0] ReadData1;
+output [DATA_WIDTH-1:0] ReadData2;
+//-------------Wires-----------------------------------
+wire [2 ** REG_SELECT_WIDTH-1:0] w_reg_to_outmux [DATA_WIDTH-1:0];
+wire [2 ** REG_SELECT_WIDTH-1:0] w_write_select;
+//-------------Other-----------------------------------
+//------------Code Starts Here-------------------------
+
+// Muxes from registers to outputs
+generate
+	genvar k; // Instance variable
+	// Generation for loop
+	for(k= 0;k< DATA_WIDTH;k= k+1)
+	begin:mux_loop
+		nbit_mux #(REG_SELECT_WIDTH) nbitmuxes1 (w_reg_to_outmux[k], ReadData1[k], ReadSelect1);
+		nbit_mux #(REG_SELECT_WIDTH) nbitmuxes2 (w_reg_to_outmux[k], ReadData2[k], ReadSelect2);
+	end
+endgenerate
+
+// Demux to select which register to write to
+nbit_demux #(REG_SELECT_WIDTH) writeselect (WriteEnable, w_write_select, WriteSelect);
+
+// Array of D Flip-flops for the registers
+generate
+	genvar i,j; // Instance variable
+	// Generation for loop
+	for(i= 0;i< DATA_WIDTH;i= i+1)
+	begin:reg_loop1
+		 for(j= 0;j< 2 ** REG_SELECT_WIDTH;j= j+1)
+		 begin:reg_loop2
+			 DFF DFFS (WriteData[i],w_reg_to_outmux[i][j],w_write_select[j],Reset,Clk);
+		 end
+	end
+endgenerate
+
+endmodule
-- 
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