From e64c18d0e30c33fe4609c881620fa937da7b8ce3 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Sun, 2 Dec 2012 12:13:10 -0500
Subject: make git repo

---
 verilog/overflow.v | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 50 insertions(+)
 create mode 100755 verilog/overflow.v

(limited to 'verilog/overflow.v')

diff --git a/verilog/overflow.v b/verilog/overflow.v
new file mode 100755
index 0000000..1662d21
--- /dev/null
+++ b/verilog/overflow.v
@@ -0,0 +1,50 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date:    22:17:44 10/04/2012 
+// Design Name: 
+// Module Name:    overflow 
+// Project Name: 
+// Target Devices: 
+// Tool versions: 
+// Description: 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module overflow(
+    output ovf,
+    input r2,
+    input r3,
+	 input r1,
+    input carry
+    );
+
+// overflow occurs (in subtraction) only when the signs are different
+// for r2 - r3
+// if r2 is negative, and r3 is potitive, will overflow to positive
+// so cout would be 0
+// if r2 is positive and r3 is negative, will overflow to negative
+// so cout would be 1
+
+
+wire r2pos, r3pos, r1pos, nsout;
+wire aw1, aw2;
+
+not n1(r2pos, r2); // positive if not r2
+not n2(r3pos, r3); // "" "" "" r3
+not n3(r1pos, r1);
+not n4(nsout, carry); 
+
+and a1(aw1, r2, r3pos, r1pos,carry); // negative - positive = bigger negative and can overflow
+and a2(aw2, r2pos, r3, r1, nsout); // pos - neg = pos
+
+or o1(ovf, aw1, aw2);
+
+endmodule
-- 
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