From e64c18d0e30c33fe4609c881620fa937da7b8ce3 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Sun, 2 Dec 2012 12:13:10 -0500 Subject: make git repo --- verilog/slt.v | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100755 verilog/slt.v (limited to 'verilog/slt.v') diff --git a/verilog/slt.v b/verilog/slt.v new file mode 100755 index 0000000..2501a07 --- /dev/null +++ b/verilog/slt.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 10:49:01 10/05/2012 +// Design Name: +// Module Name: slt +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module slt( + output out, + input r2, + input r3, + input signres, + input carryres + ); + +// r2 is less than r3 if the result of subtraction is negative +// or if it's positive and there's overflow + +wire ovfw, novfw, pos; + +overflow ovf(ovfw, r2, r3, signres, carryres); +not n1(novfw, ovfw); +not n2(pos, signres); + +wire aw1, aw2; + +and a1(aw1, signres, novfw); +and a2(aw2, pos, ovfw); + +or o1(out, aw1, aw2); + +endmodule -- cgit v1.2.3