From e64c18d0e30c33fe4609c881620fa937da7b8ce3 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Sun, 2 Dec 2012 12:13:10 -0500 Subject: make git repo --- verilog/xor.v | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100755 verilog/xor.v (limited to 'verilog/xor.v') diff --git a/verilog/xor.v b/verilog/xor.v new file mode 100755 index 0000000..0282080 --- /dev/null +++ b/verilog/xor.v @@ -0,0 +1,40 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12:20:45 10/04/2012 +// Design Name: +// Module Name: xor +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module xor_custom( + output o, + input a, + input b + ); + +wire na, nb; +wire aw1, aw2; +// xor (a,b) = ab' + a'b + +not n1(na, a); +not n2(nb, b); + +and a1(aw1, a, nb); +and a2(aw2, na, b); + +or o1(o, aw1, aw2); + + +endmodule -- cgit v1.2.3