`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    12:44:24 10/04/2012 
// Design Name: 
// Module Name:    cin_choice 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
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module cin_choice(
    output cin,
    input [2:0] op
    );

// we only want non-zero cin if we're subtracting.
// Subtraction is used in both sub and slt, so we have two cases
// 011 and 111. output is 1 for these and 0 for others 

// This is equivalent to a'bc + abc (where a, b, c are bits in op)

wire notw, subw, sltw;
not n1(notw, op[2]);

and sub_choose(subw, notw, op[1], op[0]);
and slt_choose(sltw, op[2], op[1], op[0]);
or choose(cin, sltw, subw);

endmodule