`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    23:27:42 10/21/2012 
// Design Name: 
// Module Name:    datapath 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module datapath(
     aluout, // the output from the alu
     instruction, // the instruction to execute
	  clk,
	  reset
    );
input clk, reset;
	 
parameter BITS = 32; // size of ALU operations and registers
parameter RSELW = 5; // bits required to select a register
parameter DEPTH = 3; // pipeline depth

input [31:0] instruction;
output [BITS-1:0] aluout;

wire [RSELW-1:0] rsel1, rsel2; // read selectors
wire [RSELW-1:0] wsel, wsel1, wsel2; // write selectors
wire [2:0] alu_op;
wire [15:0] immediate;

// stage 1 handles decoding and register file select signals
Stage1 #(BITS,RSELW,DEPTH) s1(
	.type(op_type),
	.alu_op(alu_op),
	.r1sel(wsel1),
	.r2sel(rsel1),
	.r3sel(rsel2),
	.imm(immediate),
	.instr(instruction),
	.clk(clk),
	.reset(reset)
);

// the registers
wire [BITS-1:0] data1, data2;
nbit_register_file #(RSELW,BITS) regfile(
	.WriteData(aluout),
	.ReadData1(data1),
	.ReadData2(data2),
	.ReadSelect1(rsel1),
	.ReadSelect2(rsel2),
	.WriteSelect(wsel[RSELW-1:0]),
	.WriteEnable(1'b1),
	.Reset(reset),
	.Clk(clk)
);

wire [BITS-1:0] operand1, operand2;
wire [2:0] alu_op_out;
Stage2 #(BITS, RSELW) s2(
	.operand1(operand1),
	.operand2(operand2),
	.wout(wsel2),
	.alu_op_out(alu_op_out),
	.op_type(op_type),
	.alu_op_in(alu_op),
	.data1(data1),
	.data2(data2),
	.immediate(immediate),
	.win(wsel1),
	.clk(clk),
	.reset(reset)
);

wire [BITS-1:0] alu_result;
alu #(BITS) a(
	.r1(alu_result),
	.r2(operand1),
	.r3(operand2),
	.aluop(alu_op_out)
);

Stage3 #(BITS,RSELW) s3(
	.alu_in(alu_result),
	.alu_out(aluout),
	.wsel_in(wsel2),
	.wsel_out(wsel),
	.clk(clk),
	.reset(reset)
);
endmodule