`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:24:15 10/04/2012 
// Design Name: 
// Module Name:    fa 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module fa(
    output sum,
    output cout,
    input a,
    input b,
    input cin
    );


wire s1, s2, s3, s4; // sum wires
wire c1, c2, c3; // carry wires
wire ia, ib, ic; // inverted wires

// invert wires ad needed for the sum
not n1(ia, a);
not n2(ib, b);
not n3(ic, cin);

// SUM CALCULATION

// compute relevant minterms
and a1(s1, ia, ib, cin);
and a2(s2, ia, b, ic);
and a3(s3, a, ib, ic);
and a4(s4, a, b, cin);

// or minterm results
or o1(sum, s1, s2, s3, s4);

// CARRY CALCULATION

// compute minterms
and ca1(c1, a, b);
and ca2(c2, a, cin);
and ca3(c3, b, cin);

// or results
or o2(cout, c1, c2, c3); 


endmodule