`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    10:49:01 10/05/2012 
// Design Name: 
// Module Name:    slt 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module slt(
    output out,
    input r2,
    input r3,
    input signres,
    input carryres
    );

// r2 is less than r3 if the result of subtraction is negative
// or if it's positive and there's overflow

wire ovfw, novfw, pos;

overflow ovf(ovfw, r2, r3, signres, carryres);
not n1(novfw, ovfw);
not n2(pos, signres);

wire aw1, aw2;

and a1(aw1, signres, novfw);
and a2(aw2, pos, ovfw);

or o1(out, aw1, aw2);

endmodule