`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   23:34:01 10/04/2012
// Design Name:   toplevel
// Module Name:   /ad/eng/users/m/g/mgabed/Documents/ec413/mgabed-lab4/test_alu.v
// Project Name:  mgabed-lab4
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: toplevel
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_alu;

	// Inputs
	reg [31:0] r2;
	reg [31:0] r3;
	reg [2:0] aluop;
	reg reset;
	reg clk;

	// Outputs
	wire [31:0] r1;

	// Instantiate the Unit Under Test (UUT)
	toplevel uut (
		.r1(r1), 
		.r2(r2), 
		.r3(r3), 
		.aluop(aluop), 
		.reset(reset), 
		.clk(clk)
	);

	initial begin
		// Initialize Inputs
		r2 = 0;
		r3 = 0;
		aluop = 0;
		reset = 0;
		clk = 1;

		// Wait 100 ns for global reset to finish
		#100;
	
		// Add stimulus here
		fork
		begin
			// test MOV
			aluop = 3'b0;
			r2 = 391; #2;
			r2 = 81283; #2;
			r3 = 3281; r2 = 1; #2;
			r2 = 0; #2;
			#20;
			
			// test NOT
			aluop = 3'b1;
			r2 = 391; #2;
			r2 = 81835; #2;
			r2 = 32'b110101011; #2;
			#20;
			
			// test ADD
			aluop = 3'b010;
			r2 = 20; r3 = 50; #2;
			r2 = -18; r3 = 188; #2;
			r2 = 0; r3 = 818; #2;
			r2 = 8184803; r3 =818501028; #2;
			#20;
			
			// test SUB
			aluop = 3'b011;
			r2 = 180; r3 = 170; #2;
			r2 = 50; r3 = 90; #2;
			r2 = -50; r3 = -150; #2;
			#20;
			
			// test OR
			aluop = 3'b100;
			r2 = 32'b01101001; r3 = 32'b10010110; #2;
			r2 = 18581; r3 = 18204; #2;
			#20;
			
			// test AND
			aluop = 3'b101;
			r2 = 32'b10101010; r3 = 23'b11001100; #2;
			r2 = 8101; r2 = 192189258; #2;
			#20;
			
			// test XOR
			aluop = 3'b110;
			r2 = 32'b11110011; r3 = 32'b11000011; #2;
			r2 = 182381052; r3 = 19285; #2;
			#20;
			
			// test SLT
			aluop = 3'b111;
			r2 = 500; r3 = 40; #2;
			r2 = -5; r3 = 100; #2;
			r2 = 1; r3 = 5; #2;
			r2 = 32'hfffffff0; r3 = 189; #2;
			r2 = 0; r3 = 0; #2;
			r2 = 32'hf0000000; r3 = 32'hf0000001; #2;
			r2 = 32'h7fffffff; r3 = 32'h80000000; #2;

			#20;
		end
		
		while (1) begin
			clk = ~clk; #1;
		end
		join
	end
      
endmodule