`timescale 1ns / 1ps
// FSM module
//
// drives the data path through multiple cycles

module fsm(
  output [3:0] state,
  input [2:0] instrtype,
  input rst,
  input clk
);

`include "params.v"

reg [3:0] state, nextstate;

always @(*) begin
  if (rst) begin
    nextstate = FETCH;
  end else begin
    case (state)
      FETCH: nextstate = DECODE;
      DECODE: if (instrtype == IINSTR || instrtype == RINSTR)
                nextstate = ALUOP;
              else if (instrtype == MEMRINSTR || instrtype == MEMWINSTR)
                nextstate = MEMCALC;
              else if (instrtype == BRINSTR)
                nextstate = BRANCH;
              else if (instrtype == JINSTR)
                nextstate = JUMP;
      MEMCALC: if (instrtype == MEMWINSTR)
                 nextstate = MEMWRITE;
               else if (instrtype == MEMRINSTR)
                  nextstate = MEMREAD;
      MEMWRITE: nextstate = FETCH;
      MEMREAD: nextstate = MEMSTORE;
      MEMSTORE: nextstate <= FETCH;
      ALUOP: nextstate = ALUSTORE;
      ALUSTORE: nextstate = FETCH;
      BRANCH: nextstate = FETCH;
      JUMP: nextstate = FETCH;
    endcase
  end
end

always @(posedge clk or posedge rst) begin
  state <= rst ? FETCH : nextstate;
end

endmodule