`timescale 1ns / 1ps

module test_fsm;

`include "params.v"

reg clk, rst;
reg [2:0] itype;
wire [3:0] state;

fsm uut(
  .state(state),
  .instrtype(itype),
  .clk(clk),
  .rst(rst)
);

initial begin
  //$dumpfile("test_fsm.vcd");
  //$dumpvars(0, uut);
  clk = 0; rst = 0; itype = RINSTR;
  #100;
  #19; rst = 1; #1; rst = 0;
  itype = RINSTR;
  #19; rst = 1; #1; rst = 0;
  itype = MEMRINSTR;
  #19; rst = 1; #1; rst = 0;
  itype = MEMWINSTR;
  #19; rst = 1; #1; rst = 0;
  itype = BRINSTR;
  #19; rst = 1; #1; rst = 0;
  itype = JINSTR;
  #19; rst = 1; #1; rst = 0;
  #100;
  //$finish;
end

always begin
  clk = ~clk; #1;
end

endmodule