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Diffstat (limited to 'CountdownController.v')
-rw-r--r-- | CountdownController.v | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/CountdownController.v b/CountdownController.v new file mode 100644 index 0000000..b06fa4b --- /dev/null +++ b/CountdownController.v @@ -0,0 +1,79 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:21:11 03/16/2012 +// Design Name: +// Module Name: CountdownController +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module CountdownController( + input btnA, + input btnB, + input btnC, + input clk, + input rst, + output [6:0] ssd, + output [3:0] AN + ); + +reg [6:0] ssd; +reg [3:0] AN; + +wire [6:0] ssdo; +wire [3:0] ANo; + +// clocks +wire seconds; +wire dbclk; +wire dispclk; + +// buttons +wire a, b; + +// bcd things +wire [3:0] ad, bd; +wire [3:0] ado, bdo, cdo; + +// time +wire [7:0] init; +wire [7:0] tout; + +ClockDivider dbc(.count(100), .rst(rst), .clk_in(clk), .clk_out(dbclk)); +ClockDivider sec(.count(100), .rst(rst), .clk_in(clk), .clk_out(seconds)); +ClockDivider dcc(.count(50), .rst(rst), .clk_in(clk), .clk_out(dispclk)); + +debouncer dbA(.dout(a), .din(btnA), .rst(rst), .clk_1M(dbclk)); +debouncer dbB(.dout(b), .din(btnB), .rst(rst), .clk_1M(dbclk)); + +//Increment inc1(.value(ad), .btn(a)); +//Increment inc2(.value(bd), .btn(b)); + +Increment inc1(.value(ad), .btn(btnA)); +Increment inc2(.value(bd), .btn(btnB)); + +BCD2Bin bcd2b(.hun(0), .ten(ad), .one(bd), .bin(init)); + +Countdown cntdwn(.t(tout), .rst(rst), .init(init), .clk_1hz(seconds), .start(btnC)); + +Bin2BCD b2bcb(.hun(cdo), .ten(ado), .one(bdo), .bin(tout)); + +DisplayController dispcont(.result(ssdo), .AN(ANo), .A(ado), .B(bdo), .clk_in(dispclk), .rst(rst)); + + +always @(posedge clk) begin + ssd <= ssdo; + AN <= ANo; +end +endmodule |