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Diffstat (limited to 'verilog/clock_delay.v')
-rwxr-xr-x | verilog/clock_delay.v | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/verilog/clock_delay.v b/verilog/clock_delay.v new file mode 100755 index 0000000..048b8ef --- /dev/null +++ b/verilog/clock_delay.v @@ -0,0 +1,52 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 22:02:54 10/21/2012 +// Design Name: +// Module Name: clock_delay +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module clock_delay( + out, + in, + clk, + reset + ); + +input clk, reset; + +parameter TIME=3; // number of bits to save +parameter BITS=5; // number of bits per tick + +input [BITS-1:0] in; +output [BITS-1:0] out; + +wire [BITS-1:0] connector [0:TIME+1]; + +assign connector[0] = in; +assign out = connector[TIME+1]; + + +generate +genvar i; + +for (i = 1; i <= TIME+1; i = i + 1) begin:reggen + nbit_reg #(BITS) nb(.nD(connector[i-1]), .nQ(connector[i]), .Write(1'b1), .Reset(reset), .Clk(clk)); +end + +endgenerate + + +endmodule |