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Diffstat (limited to 'verilog/nbit_reg.v')
-rwxr-xr-x | verilog/nbit_reg.v | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/verilog/nbit_reg.v b/verilog/nbit_reg.v new file mode 100755 index 0000000..892d42c --- /dev/null +++ b/verilog/nbit_reg.v @@ -0,0 +1,23 @@ +//n bit register
+
+module nbit_reg(nD, // Register Input + nQ, // Register Output + Write, // Only accept input when this is set + Reset, // Synchronous Reset + Clk); // Clock + +// Specifies the register data width. +parameter DATA_WIDTH = 32; + +//-------------Input Ports----------------------------- +input [DATA_WIDTH-1:0] nD; +input Write; +input Reset; +input Clk; +//-------------Output Ports---------------------------- +output [DATA_WIDTH-1:0] nQ; +//-------------Wires----------------------------------- +//-------------Other----------------------------------- +//------------Code Starts Here------------------------- +DFF DFFs[DATA_WIDTH-1:0] (nD, nQ, Write, Reset, Clk);
+endmodule
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