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Diffstat (limited to 'verilog/xor.v')
-rwxr-xr-x | verilog/xor.v | 40 |
1 files changed, 40 insertions, 0 deletions
diff --git a/verilog/xor.v b/verilog/xor.v new file mode 100755 index 0000000..0282080 --- /dev/null +++ b/verilog/xor.v @@ -0,0 +1,40 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 12:20:45 10/04/2012 +// Design Name: +// Module Name: xor +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module xor_custom( + output o, + input a, + input b + ); + +wire na, nb; +wire aw1, aw2; +// xor (a,b) = ab' + a'b + +not n1(na, a); +not n2(nb, b); + +and a1(aw1, a, nb); +and a2(aw2, na, b); + +or o1(o, aw1, aw2); + + +endmodule |