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+Release 13.3 - xst O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
+--> Parameter TMPDIR set to xst/projnav.tmp
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.12 secs
+ 
+--> Parameter xsthdpdir set to xst
+
+
+Total REAL time to Xst completion: 0.00 secs
+Total CPU time to Xst completion: 0.13 secs
+ 
+--> Reading design: ALU.prj
+
+TABLE OF CONTENTS
+  1) Synthesis Options Summary
+  2) HDL Parsing
+  3) HDL Elaboration
+  4) HDL Synthesis
+       4.1) HDL Synthesis Report
+  5) Advanced HDL Synthesis
+       5.1) Advanced HDL Synthesis Report
+  6) Low Level Synthesis
+  7) Partition Report
+  8) Design Summary
+       8.1) Primitive and Black Box Usage
+       8.2) Device utilization summary
+       8.3) Partition Resource Summary
+       8.4) Timing Report
+            8.4.1) Clock Information
+            8.4.2) Asynchronous Control Signals Information
+            8.4.3) Timing Summary
+            8.4.4) Timing Details
+            8.4.5) Cross Clock Domains Report
+
+
+=========================================================================
+*                      Synthesis Options Summary                        *
+=========================================================================
+---- Source Parameters
+Input File Name                    : "ALU.prj"
+Ignore Synthesis Constraint File   : NO
+
+---- Target Parameters
+Output File Name                   : "ALU"
+Output Format                      : NGC
+Target Device                      : xc6slx16-3-csg324
+
+---- Source Options
+Top Module Name                    : ALU
+Automatic FSM Extraction           : YES
+FSM Encoding Algorithm             : Auto
+Safe Implementation                : No
+FSM Style                          : LUT
+RAM Extraction                     : Yes
+RAM Style                          : Auto
+ROM Extraction                     : Yes
+Shift Register Extraction          : YES
+ROM Style                          : Auto
+Resource Sharing                   : YES
+Asynchronous To Synchronous        : NO
+Shift Register Minimum Size        : 2
+Use DSP Block                      : Auto
+Automatic Register Balancing       : No
+
+---- Target Options
+LUT Combining                      : Auto
+Reduce Control Sets                : Auto
+Add IO Buffers                     : YES
+Global Maximum Fanout              : 100000
+Add Generic Clock Buffer(BUFG)     : 16
+Register Duplication               : YES
+Optimize Instantiated Primitives   : NO
+Use Clock Enable                   : Auto
+Use Synchronous Set                : Auto
+Use Synchronous Reset              : Auto
+Pack IO Registers into IOBs        : Auto
+Equivalent register Removal        : YES
+
+---- General Options
+Optimization Goal                  : Speed
+Optimization Effort                : 1
+Power Reduction                    : NO
+Keep Hierarchy                     : No
+Netlist Hierarchy                  : As_Optimized
+RTL Output                         : Yes
+Global Optimization                : AllClockNets
+Read Cores                         : YES
+Write Timing Constraints           : NO
+Cross Clock Analysis               : NO
+Hierarchy Separator                : /
+Bus Delimiter                      : <>
+Case Specifier                     : Maintain
+Slice Utilization Ratio            : 100
+BRAM Utilization Ratio             : 100
+DSP48 Utilization Ratio            : 100
+Auto BRAM Packing                  : NO
+Slice Utilization Ratio Delta      : 5
+
+=========================================================================
+
+
+=========================================================================
+*                          HDL Parsing                                  *
+=========================================================================
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_3.vf" into library work
+Parsing module <Negate_3>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_2.vf" into library work
+Parsing module <Negate_2>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_1.vf" into library work
+Parsing module <Negate_1>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_0.vf" into library work
+Parsing module <Negate_0>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo_3.vf" into library work
+Parsing module <Modulo_3>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo_1.vf" into library work
+Parsing module <Modulo_1>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo_0.vf" into library work
+Parsing module <Modulo_0>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_3.vf" into library work
+Parsing module <Divide_3>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_2.vf" into library work
+Parsing module <Divide_2>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_1.vf" into library work
+Parsing module <Divide_1>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_0.vf" into library work
+Parsing module <Divide_0>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\sev_seg_disp.vf" into library work
+Parsing module <sev_seg_disp>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate.vf" into library work
+Parsing module <Negate_3_MUSER_Negate>.
+Parsing module <Negate_1_MUSER_Negate>.
+Parsing module <Negate_2_MUSER_Negate>.
+Parsing module <Negate_0_MUSER_Negate>.
+Parsing module <Negate>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo.vf" into library work
+Parsing module <Modulo_0_MUSER_Modulo>.
+Parsing module <Modulo_1_MUSER_Modulo>.
+Parsing module <Modulo_3_MUSER_Modulo>.
+Parsing module <Modulo>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide.vf" into library work
+Parsing module <Divide_1_MUSER_Divide>.
+Parsing module <Divide_2_MUSER_Divide>.
+Parsing module <Divide_3_MUSER_Divide>.
+Parsing module <Divide_0_MUSER_Divide>.
+Parsing module <Divide>.
+Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\ALU.vf" into library work
+Parsing module <M4_1E_HXILINX_ALU>.
+Parsing module <sev_seg_disp_MUSER_ALU>.
+Parsing module <Negate_3_MUSER_ALU>.
+Parsing module <Negate_1_MUSER_ALU>.
+Parsing module <Negate_2_MUSER_ALU>.
+Parsing module <Negate_0_MUSER_ALU>.
+Parsing module <Negate_MUSER_ALU>.
+Parsing module <Modulo_0_MUSER_ALU>.
+Parsing module <Modulo_1_MUSER_ALU>.
+Parsing module <Modulo_3_MUSER_ALU>.
+Parsing module <Modulo_MUSER_ALU>.
+Parsing module <Divide_1_MUSER_ALU>.
+Parsing module <Divide_2_MUSER_ALU>.
+Parsing module <Divide_3_MUSER_ALU>.
+Parsing module <Divide_0_MUSER_ALU>.
+Parsing module <Divide_MUSER_ALU>.
+Parsing module <ALU>.
+
+=========================================================================
+*                            HDL Elaboration                            *
+=========================================================================
+
+Elaborating module <ALU>.
+
+Elaborating module <Divide_MUSER_ALU>.
+
+Elaborating module <Divide_1_MUSER_ALU>.
+
+Elaborating module <AND4>.
+
+Elaborating module <OR3>.
+
+Elaborating module <AND2>.
+
+Elaborating module <OR2>.
+
+Elaborating module <INV>.
+
+Elaborating module <Divide_2_MUSER_ALU>.
+
+Elaborating module <AND3>.
+
+Elaborating module <Divide_3_MUSER_ALU>.
+
+Elaborating module <NOR3>.
+
+Elaborating module <Divide_0_MUSER_ALU>.
+
+Elaborating module <Modulo_MUSER_ALU>.
+
+Elaborating module <Modulo_3_MUSER_ALU>.
+
+Elaborating module <Modulo_1_MUSER_ALU>.
+
+Elaborating module <NAND4>.
+
+Elaborating module <Modulo_0_MUSER_ALU>.
+
+Elaborating module <XNOR2>.
+
+Elaborating module <NAND3>.
+
+Elaborating module <Negate_MUSER_ALU>.
+
+Elaborating module <Negate_0_MUSER_ALU>.
+
+Elaborating module <Negate_1_MUSER_ALU>.
+
+Elaborating module <Negate_2_MUSER_ALU>.
+
+Elaborating module <Negate_3_MUSER_ALU>.
+
+Elaborating module <NAND2>.
+
+Elaborating module <M4_1E_HXILINX_ALU>.
+
+Elaborating module <VCC>.
+
+Elaborating module <sev_seg_disp_MUSER_ALU>.
+
+Elaborating module <BUF>.
+
+Elaborating module <GND>.
+
+Elaborating module <OR5>.
+
+Elaborating module <OR4>.
+
+Elaborating module <XOR2>.
+
+=========================================================================
+*                           HDL Synthesis                               *
+=========================================================================
+
+Synthesizing Unit <ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Set property "HU_SET = XLXI_4_0" for instance <XLXI_4>.
+    Set property "HU_SET = XLXI_5_1" for instance <XLXI_5>.
+    Set property "HU_SET = XLXI_6_2" for instance <XLXI_6>.
+    Set property "HU_SET = XLXI_7_3" for instance <XLXI_7>.
+    Summary:
+	no macro.
+Unit <ALU> synthesized.
+
+Synthesizing Unit <Divide_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <Divide_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Divide_1_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <Divide_1_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Divide_2_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <Divide_2_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Divide_3_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <Divide_3_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Divide_0_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+WARNING:Xst:647 - Input <b2> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+    Summary:
+	no macro.
+Unit <Divide_0_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Modulo_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <Modulo_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Modulo_3_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <Modulo_3_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Modulo_1_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <Modulo_1_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Modulo_0_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+WARNING:Xst:647 - Input <b3> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+    Summary:
+	no macro.
+Unit <Modulo_0_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Negate_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <Negate_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Negate_0_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <Negate_0_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Negate_1_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <Negate_1_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Negate_2_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <Negate_2_MUSER_ALU> synthesized.
+
+Synthesizing Unit <Negate_3_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <Negate_3_MUSER_ALU> synthesized.
+
+Synthesizing Unit <M4_1E_HXILINX_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Found 1-bit 4-to-1 multiplexer for signal <S1_D3_Mux_0_o> created at line 44.
+    Summary:
+	inferred   2 Multiplexer(s).
+Unit <M4_1E_HXILINX_ALU> synthesized.
+
+Synthesizing Unit <sev_seg_disp_MUSER_ALU>.
+    Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf".
+    Summary:
+	no macro.
+Unit <sev_seg_disp_MUSER_ALU> synthesized.
+
+=========================================================================
+HDL Synthesis Report
+
+Macro Statistics
+# Multiplexers                                         : 8
+ 1-bit 2-to-1 multiplexer                              : 4
+ 1-bit 4-to-1 multiplexer                              : 4
+
+=========================================================================
+
+=========================================================================
+*                       Advanced HDL Synthesis                          *
+=========================================================================
+
+
+=========================================================================
+Advanced HDL Synthesis Report
+
+Macro Statistics
+# Multiplexers                                         : 8
+ 1-bit 2-to-1 multiplexer                              : 4
+ 1-bit 4-to-1 multiplexer                              : 4
+
+=========================================================================
+
+=========================================================================
+*                         Low Level Synthesis                           *
+=========================================================================
+
+Optimizing unit <ALU> ...
+
+Optimizing unit <sev_seg_disp_MUSER_ALU> ...
+
+Optimizing unit <M4_1E_HXILINX_ALU> ...
+
+Mapping all equations...
+Building and optimizing final netlist ...
+Found area constraint ratio of 100 (+ 5) on block ALU, actual ratio is 0.
+
+Final Macro Processing ...
+
+=========================================================================
+Final Register Report
+
+Found no macro
+=========================================================================
+
+=========================================================================
+*                           Partition Report                            *
+=========================================================================
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+=========================================================================
+*                            Design Summary                             *
+=========================================================================
+
+Top Level Output File Name         : ALU.ngc
+
+Primitive and Black Box Usage:
+------------------------------
+# BELS                             : 125
+#      AND2                        : 22
+#      AND3                        : 21
+#      AND4                        : 2
+#      BUF                         : 4
+#      GND                         : 1
+#      INV                         : 45
+#      LUT6                        : 4
+#      OR2                         : 7
+#      OR3                         : 10
+#      OR4                         : 4
+#      OR5                         : 1
+#      VCC                         : 1
+#      XNOR2                       : 2
+#      XOR2                        : 1
+# IO Buffers                       : 18
+#      IBUF                        : 6
+#      OBUF                        : 12
+# Logical                          : 4
+#      NAND2                       : 1
+#      NAND3                       : 1
+#      NAND4                       : 1
+#      NOR3                        : 1
+
+Device utilization summary:
+---------------------------
+
+Selected Device : 6slx16csg324-3 
+
+
+Slice Logic Utilization: 
+ Number of Slice LUTs:                   49  out of   9112     0%  
+    Number used as Logic:                49  out of   9112     0%  
+
+Slice Logic Distribution: 
+ Number of LUT Flip Flop pairs used:     49
+   Number with an unused Flip Flop:      49  out of     49   100%  
+   Number with an unused LUT:             0  out of     49     0%  
+   Number of fully used LUT-FF pairs:     0  out of     49     0%  
+   Number of unique control sets:         0
+
+IO Utilization: 
+ Number of IOs:                          18
+ Number of bonded IOBs:                  18  out of    232     7%  
+
+Specific Feature Utilization:
+
+---------------------------
+Partition Resource Summary:
+---------------------------
+
+  No Partitions were found in this design.
+
+---------------------------
+
+
+=========================================================================
+Timing Report
+
+NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
+      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
+      GENERATED AFTER PLACE-and-ROUTE.
+
+Clock Information:
+------------------
+No clock signals found in this design
+
+Asynchronous Control Signals Information:
+----------------------------------------
+No asynchronous control signals found in this design
+
+Timing Summary:
+---------------
+Speed Grade: -3
+
+   Minimum period: No path found
+   Minimum input arrival time before clock: No path found
+   Maximum output required time after clock: No path found
+   Maximum combinational path delay: 16.544ns
+
+Timing Details:
+---------------
+All values displayed in nanoseconds (ns)
+
+=========================================================================
+Timing constraint: Default path analysis
+  Total number of paths / destination ports: 1495 / 8
+-------------------------------------------------------------------------
+Delay:               16.544ns (Levels of Logic = 13)
+  Source:            D (PAD)
+  Destination:       d_out (PAD)
+
+  Data Path: D to d_out
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     IBUF:I->O            24   1.222   1.172  D_IBUF (D_IBUF)
+     INV:I->O              1   0.568   0.944  XLXI_1/XLXI_8/XLXI_9 (XLXI_1/XLXI_8/XLXN_17)
+     AND2:I0->O            1   0.203   0.924  XLXI_1/XLXI_8/XLXI_3 (XLXI_1/XLXI_8/XLXN_1)
+     OR3:I1->O             1   0.223   0.944  XLXI_1/XLXI_8/XLXI_2 (XLXI_1/XLXI_8/XLXN_2)
+     AND2:I0->O            1   0.203   0.924  XLXI_1/XLXI_8/XLXI_4 (XLXI_1/XLXI_8/XLXN_4)
+     OR2:I1->O             1   0.223   0.580  XLXI_1/XLXI_8/XLXI_5 (XLXN_35)
+     begin scope: 'XLXI_6:D2'
+     LUT6:I5->O            9   0.205   0.829  Mmux_O11 (O)
+     end scope: 'XLXI_6:O'
+     INV:I->O              8   0.568   1.167  XLXI_9/XLXI_39 (XLXI_9/C_BAR)
+     AND3:I0->O            1   0.203   0.944  XLXI_9/XLXI_51 (XLXI_9/XLXN_114)
+     OR4:I0->O             1   0.203   0.579  XLXI_9/XLXI_52 (XLXI_9/XLXN_156)
+     INV:I->O              1   0.568   0.579  XLXI_9/XLXI_69 (d_out_OBUF)
+     OBUF:I->O                 2.571          d_out_OBUF (d_out)
+    ----------------------------------------
+    Total                     16.544ns (6.960ns logic, 9.584ns route)
+                                       (42.1% logic, 57.9% route)
+
+=========================================================================
+
+Cross Clock Domains Report:
+--------------------------
+
+=========================================================================
+
+
+Total REAL time to Xst completion: 8.00 secs
+Total CPU time to Xst completion: 7.97 secs
+ 
+--> 
+
+Total memory usage is 253940 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings :    2 (   0 filtered)
+Number of infos    :    0 (   0 filtered)
+