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| author | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:19 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:19 -0500 |
| commit | 57738e75e221fe61a8f87270b430c0f1c0b8ead5 (patch) | |
| tree | 8ace7cfb1f8b7330e45dad06e4a21efeb2cadd64 /ALU.vf | |
| download | ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.tar.gz ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.tar.bz2 ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.zip | |
initial commit
Diffstat (limited to 'ALU.vf')
| -rwxr-xr-x | ALU.vf | 974 |
1 files changed, 974 insertions, 0 deletions
@@ -0,0 +1,974 @@ +////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version : 13.3
+// \ \ Application : sch2hdl
+// / / Filename : ALU.vf
+// /___/ /\ Timestamp : 02/15/2012 15:00:05
+// \ \ / \
+// \___\/\___\
+//
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/ALU.vf" -w "X:/My Documents/ec311/lab1/ALU.sch"
+//Design Name: ALU
+//Device: spartan6
+//Purpose:
+// This verilog netlist is translated from an ECS schematic.It can be
+// synthesized and simulated, but it should not be modified.
+//
+`timescale 100 ps / 10 ps
+
+module M4_1E_HXILINX_ALU (O, D0, D1, D2, D3, E, S0, S1);
+
+
+ output O;
+
+ input D0;
+ input D1;
+ input D2;
+ input D3;
+ input E;
+ input S0;
+ input S1;
+
+ reg O;
+
+ always @ ( D0 or D1 or D2 or D3 or E or S0 or S1)
+ begin
+ if(!E)
+ O <= 1'b0;
+ else
+ begin
+ case({S1,S0})
+ 2'b00 : O <= D0;
+ 2'b01 : O <= D1;
+ 2'b10 : O <= D2;
+ 2'b11 : O <= D3;
+ endcase
+ end
+ end
+
+endmodule
+`timescale 1ns / 1ps
+
+module sev_seg_disp_MUSER_ALU(A,
+ B,
+ C,
+ D,
+ AN0,
+ AN1,
+ AN2,
+ AN3,
+ a_out,
+ b_out,
+ c_out,
+ d_out,
+ e_out,
+ f_out,
+ g_out,
+ sign);
+
+ input A;
+ input B;
+ input C;
+ input D;
+ output AN0;
+ output AN1;
+ output AN2;
+ output AN3;
+ output a_out;
+ output b_out;
+ output c_out;
+ output d_out;
+ output e_out;
+ output f_out;
+ output g_out;
+ output sign;
+
+ wire A_BAR;
+ wire B_BAR;
+ wire C_BAR;
+ wire D_BAR;
+ wire XLXN_14;
+ wire XLXN_24;
+ wire XLXN_61;
+ wire XLXN_62;
+ wire XLXN_63;
+ wire XLXN_64;
+ wire XLXN_65;
+ wire XLXN_91;
+ wire XLXN_92;
+ wire XLXN_93;
+ wire XLXN_94;
+ wire XLXN_105;
+ wire XLXN_113;
+ wire XLXN_114;
+ wire XLXN_125;
+ wire XLXN_126;
+ wire XLXN_128;
+ wire XLXN_129;
+ wire XLXN_130;
+ wire XLXN_131;
+ wire XLXN_145;
+ wire XLXN_146;
+ wire XLXN_147;
+ wire XLXN_148;
+ wire XLXN_149;
+ wire XLXN_151;
+ wire XLXN_155;
+ wire XLXN_156;
+ wire XLXN_158;
+ wire XLXN_160;
+ wire XLXN_162;
+ wire XLXN_165;
+
+ BUF XLXI_5 (.I(XLXN_14),
+ .O(AN0));
+ BUF XLXI_6 (.I(XLXN_14),
+ .O(AN1));
+ BUF XLXI_7 (.I(XLXN_14),
+ .O(AN2));
+ BUF XLXI_8 (.I(XLXN_24),
+ .O(AN3));
+ GND XLXI_11 (.G(XLXN_24));
+ VCC XLXI_12 (.P(XLXN_14));
+ AND3 XLXI_30 (.I0(B),
+ .I1(C_BAR),
+ .I2(D),
+ .O(XLXN_61));
+ AND3 XLXI_31 (.I0(A_BAR),
+ .I1(D),
+ .I2(C),
+ .O(XLXN_62));
+ AND2 XLXI_32 (.I0(B_BAR),
+ .I1(D_BAR),
+ .O(XLXN_63));
+ AND2 XLXI_33 (.I0(C),
+ .I1(D_BAR),
+ .O(XLXN_64));
+ OR5 XLXI_34 (.I0(XLXN_65),
+ .I1(XLXN_64),
+ .I2(XLXN_63),
+ .I3(XLXN_62),
+ .I4(XLXN_61),
+ .O(XLXN_149));
+ AND2 XLXI_35 (.I0(B_BAR),
+ .I1(A),
+ .O(XLXN_65));
+ INV XLXI_37 (.I(A),
+ .O(A_BAR));
+ INV XLXI_38 (.I(B),
+ .O(B_BAR));
+ INV XLXI_39 (.I(C),
+ .O(C_BAR));
+ INV XLXI_40 (.I(D),
+ .O(D_BAR));
+ OR4 XLXI_41 (.I0(XLXN_94),
+ .I1(XLXN_93),
+ .I2(XLXN_92),
+ .I3(XLXN_91),
+ .O(XLXN_151));
+ XNOR2 XLXI_42 (.I0(B),
+ .I1(A),
+ .O(XLXN_91));
+ AND2 XLXI_43 (.I0(D_BAR),
+ .I1(C_BAR),
+ .O(XLXN_92));
+ AND2 XLXI_44 (.I0(B_BAR),
+ .I1(C_BAR),
+ .O(XLXN_93));
+ AND3 XLXI_45 (.I0(A_BAR),
+ .I1(D),
+ .I2(C),
+ .O(XLXN_94));
+ XOR2 XLXI_46 (.I0(B),
+ .I1(A),
+ .O(XLXN_105));
+ OR3 XLXI_47 (.I0(D),
+ .I1(C_BAR),
+ .I2(XLXN_105),
+ .O(XLXN_155));
+ AND2 XLXI_48 (.I0(D_BAR),
+ .I1(C),
+ .O(XLXN_125));
+ AND2 XLXI_49 (.I0(D_BAR),
+ .I1(B_BAR),
+ .O(XLXN_126));
+ AND2 XLXI_50 (.I0(C),
+ .I1(B_BAR),
+ .O(XLXN_113));
+ AND3 XLXI_51 (.I0(C_BAR),
+ .I1(D),
+ .I2(B),
+ .O(XLXN_114));
+ OR4 XLXI_52 (.I0(XLXN_114),
+ .I1(XLXN_113),
+ .I2(XLXN_126),
+ .I3(XLXN_125),
+ .O(XLXN_156));
+ OR2 XLXI_53 (.I0(XLXN_126),
+ .I1(XLXN_125),
+ .O(XLXN_158));
+ AND3 XLXI_54 (.I0(C_BAR),
+ .I1(B),
+ .I2(A_BAR),
+ .O(XLXN_128));
+ AND3 XLXI_55 (.I0(C),
+ .I1(B_BAR),
+ .I2(A),
+ .O(XLXN_129));
+ AND3 XLXI_56 (.I0(D_BAR),
+ .I1(B),
+ .I2(A_BAR),
+ .O(XLXN_130));
+ AND2 XLXI_57 (.I0(D_BAR),
+ .I1(C_BAR),
+ .O(XLXN_131));
+ OR4 XLXI_58 (.I0(XLXN_131),
+ .I1(XLXN_130),
+ .I2(XLXN_129),
+ .I3(XLXN_128),
+ .O(XLXN_160));
+ OR4 XLXI_60 (.I0(XLXN_148),
+ .I1(XLXN_147),
+ .I2(XLXN_146),
+ .I3(XLXN_145),
+ .O(XLXN_162));
+ AND2 XLXI_61 (.I0(C_BAR),
+ .I1(B),
+ .O(XLXN_145));
+ AND2 XLXI_62 (.I0(D_BAR),
+ .I1(C),
+ .O(XLXN_146));
+ AND2 XLXI_63 (.I0(B_BAR),
+ .I1(C),
+ .O(XLXN_147));
+ AND2 XLXI_64 (.I0(D_BAR),
+ .I1(A),
+ .O(XLXN_148));
+ INV XLXI_65 (.I(XLXN_149),
+ .O(a_out));
+ INV XLXI_66 (.I(XLXN_151),
+ .O(b_out));
+ INV XLXI_67 (.I(XLXN_155),
+ .O(c_out));
+ INV XLXI_68 (.I(XLXN_158),
+ .O(e_out));
+ INV XLXI_69 (.I(XLXN_156),
+ .O(d_out));
+ INV XLXI_70 (.I(XLXN_160),
+ .O(f_out));
+ INV XLXI_71 (.I(XLXN_162),
+ .O(g_out));
+ INV XLXI_72 (.I(A_BAR),
+ .O(XLXN_165));
+ INV XLXI_73 (.I(XLXN_165),
+ .O(sign));
+endmodule
+`timescale 1ns / 1ps
+
+module Negate_3_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_8;
+ wire XLXN_9;
+
+ OR3 XLXI_5 (.I0(b2),
+ .I1(b1),
+ .I2(b0),
+ .O(XLXN_9));
+ NAND2 XLXI_9 (.I0(XLXN_8),
+ .I1(b3),
+ .O(result));
+ INV XLXI_12 (.I(XLXN_9),
+ .O(XLXN_8));
+endmodule
+`timescale 1ns / 1ps
+
+module Negate_1_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_1;
+ wire XLXN_2;
+ wire XLXN_3;
+ wire XLXN_4;
+ wire XLXN_5;
+ wire XLXN_6;
+
+ AND2 XLXI_1 (.I0(b1),
+ .I1(XLXN_6),
+ .O(XLXN_2));
+ AND2 XLXI_2 (.I0(XLXN_5),
+ .I1(b0),
+ .O(XLXN_1));
+ AND3 XLXI_3 (.I0(XLXN_4),
+ .I1(XLXN_5),
+ .I2(b3),
+ .O(XLXN_3));
+ OR3 XLXI_4 (.I0(XLXN_3),
+ .I1(XLXN_1),
+ .I2(XLXN_2),
+ .O(result));
+ INV XLXI_5 (.I(b2),
+ .O(XLXN_4));
+ INV XLXI_6 (.I(b1),
+ .O(XLXN_5));
+ INV XLXI_7 (.I(b0),
+ .O(XLXN_6));
+endmodule
+`timescale 1ns / 1ps
+
+module Negate_2_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_7;
+ wire XLXN_9;
+ wire XLXN_10;
+ wire XLXN_12;
+ wire XLXN_16;
+ wire XLXN_17;
+
+ AND2 XLXI_1 (.I0(XLXN_7),
+ .I1(b3),
+ .O(XLXN_9));
+ AND3 XLXI_2 (.I0(b2),
+ .I1(XLXN_16),
+ .I2(XLXN_17),
+ .O(XLXN_10));
+ OR2 XLXI_3 (.I0(XLXN_10),
+ .I1(XLXN_9),
+ .O(result));
+ OR3 XLXI_4 (.I0(XLXN_12),
+ .I1(b1),
+ .I2(b0),
+ .O(XLXN_7));
+ INV XLXI_5 (.I(b2),
+ .O(XLXN_12));
+ INV XLXI_6 (.I(b1),
+ .O(XLXN_16));
+ INV XLXI_7 (.I(b0),
+ .O(XLXN_17));
+endmodule
+`timescale 1ns / 1ps
+
+module Negate_0_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_14;
+ wire XLXN_15;
+ wire XLXN_17;
+
+ AND3 XLXI_8 (.I0(b3),
+ .I1(XLXN_15),
+ .I2(XLXN_14),
+ .O(XLXN_17));
+ INV XLXI_9 (.I(b1),
+ .O(XLXN_14));
+ INV XLXI_10 (.I(b2),
+ .O(XLXN_15));
+ OR2 XLXI_12 (.I0(XLXN_17),
+ .I1(b0),
+ .O(result));
+endmodule
+`timescale 1ns / 1ps
+
+module Negate_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ out0,
+ out1,
+ out2,
+ out3);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output out0;
+ output out1;
+ output out2;
+ output out3;
+
+
+ Negate_0_MUSER_ALU XLXI_8 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out0));
+ Negate_1_MUSER_ALU XLXI_9 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out1));
+ Negate_2_MUSER_ALU XLXI_10 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out2));
+ Negate_3_MUSER_ALU XLXI_12 (.b0(b2),
+ .b1(b1),
+ .b2(b0),
+ .b3(b3),
+ .result(out3));
+endmodule
+`timescale 1ns / 1ps
+
+module Modulo_0_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_1;
+ wire XLXN_3;
+ wire XLXN_4;
+ wire XLXN_5;
+
+ XNOR2 XLXI_1 (.I0(b0),
+ .I1(b1),
+ .O(XLXN_1));
+ AND2 XLXI_2 (.I0(XLXN_1),
+ .I1(b2),
+ .O(XLXN_4));
+ NAND3 XLXI_3 (.I0(XLXN_5),
+ .I1(b1),
+ .I2(b2),
+ .O(XLXN_3));
+ OR2 XLXI_4 (.I0(XLXN_4),
+ .I1(XLXN_3),
+ .O(result));
+ INV XLXI_5 (.I(b0),
+ .O(XLXN_5));
+endmodule
+`timescale 1ns / 1ps
+
+module Modulo_1_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_1;
+ wire XLXN_2;
+ wire XLXN_3;
+ wire XLXN_5;
+ wire XLXN_6;
+ wire XLXN_7;
+ wire XLXN_18;
+ wire XLXN_19;
+ wire XLXN_20;
+ wire XLXN_21;
+ wire XLXN_22;
+ wire XLXN_23;
+ wire XLXN_24;
+
+ AND3 XLXI_1 (.I0(b1),
+ .I1(b2),
+ .I2(b3),
+ .O(XLXN_1));
+ AND3 XLXI_2 (.I0(XLXN_6),
+ .I1(XLXN_5),
+ .I2(b3),
+ .O(XLXN_2));
+ AND3 XLXI_3 (.I0(b0),
+ .I1(XLXN_7),
+ .I2(b3),
+ .O(XLXN_3));
+ OR3 XLXI_4 (.I0(XLXN_3),
+ .I1(XLXN_2),
+ .I2(XLXN_1),
+ .O(XLXN_21));
+ INV XLXI_5 (.I(b1),
+ .O(XLXN_5));
+ INV XLXI_6 (.I(b0),
+ .O(XLXN_6));
+ INV XLXI_7 (.I(b2),
+ .O(XLXN_7));
+ OR2 XLXI_9 (.I0(XLXN_20),
+ .I1(XLXN_21),
+ .O(result));
+ AND4 XLXI_11 (.I0(b0),
+ .I1(XLXN_24),
+ .I2(b2),
+ .I3(XLXN_23),
+ .O(XLXN_19));
+ OR2 XLXI_12 (.I0(XLXN_19),
+ .I1(XLXN_18),
+ .O(XLXN_20));
+ NAND4 XLXI_13 (.I0(b0),
+ .I1(XLXN_22),
+ .I2(b2),
+ .I3(b3),
+ .O(XLXN_18));
+ INV XLXI_14 (.I(b1),
+ .O(XLXN_22));
+ INV XLXI_15 (.I(b3),
+ .O(XLXN_23));
+ INV XLXI_16 (.I(b1),
+ .O(XLXN_24));
+endmodule
+`timescale 1ns / 1ps
+
+module Modulo_3_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_1;
+ wire XLXN_2;
+ wire XLXN_3;
+ wire XLXN_5;
+ wire XLXN_6;
+ wire XLXN_7;
+
+ AND3 XLXI_1 (.I0(b1),
+ .I1(b2),
+ .I2(b3),
+ .O(XLXN_1));
+ AND3 XLXI_2 (.I0(XLXN_6),
+ .I1(XLXN_5),
+ .I2(b3),
+ .O(XLXN_2));
+ AND3 XLXI_3 (.I0(b0),
+ .I1(XLXN_7),
+ .I2(b3),
+ .O(XLXN_3));
+ OR3 XLXI_4 (.I0(XLXN_3),
+ .I1(XLXN_2),
+ .I2(XLXN_1),
+ .O(result));
+ INV XLXI_5 (.I(b1),
+ .O(XLXN_5));
+ INV XLXI_6 (.I(b0),
+ .O(XLXN_6));
+ INV XLXI_7 (.I(b2),
+ .O(XLXN_7));
+endmodule
+`timescale 1ns / 1ps
+
+module Modulo_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ out0,
+ out1,
+ out2,
+ out3);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output out0;
+ output out1;
+ output out2;
+ output out3;
+
+
+ Modulo_3_MUSER_ALU XLXI_1 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out3));
+ Modulo_3_MUSER_ALU XLXI_2 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out2));
+ Modulo_1_MUSER_ALU XLXI_3 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out1));
+ Modulo_0_MUSER_ALU XLXI_4 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out0));
+endmodule
+`timescale 1ns / 1ps
+
+module Divide_1_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_1;
+ wire XLXN_2;
+ wire XLXN_4;
+ wire XLXN_5;
+ wire XLXN_8;
+ wire XLXN_13;
+ wire XLXN_16;
+ wire XLXN_17;
+
+ AND4 XLXI_1 (.I0(b3),
+ .I1(b1),
+ .I2(XLXN_8),
+ .I3(b0),
+ .O(XLXN_5));
+ OR3 XLXI_2 (.I0(XLXN_16),
+ .I1(XLXN_1),
+ .I2(XLXN_13),
+ .O(XLXN_2));
+ AND2 XLXI_3 (.I0(XLXN_17),
+ .I1(b1),
+ .O(XLXN_1));
+ AND2 XLXI_4 (.I0(XLXN_2),
+ .I1(b2),
+ .O(XLXN_4));
+ OR2 XLXI_5 (.I0(XLXN_5),
+ .I1(XLXN_4),
+ .O(result));
+ INV XLXI_6 (.I(b2),
+ .O(XLXN_8));
+ INV XLXI_7 (.I(b3),
+ .O(XLXN_13));
+ INV XLXI_8 (.I(b1),
+ .O(XLXN_16));
+ INV XLXI_9 (.I(b0),
+ .O(XLXN_17));
+endmodule
+`timescale 1ns / 1ps
+
+module Divide_2_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_1;
+ wire XLXN_2;
+ wire XLXN_3;
+ wire XLXN_7;
+
+ OR3 XLXI_1 (.I0(XLXN_1),
+ .I1(XLXN_7),
+ .I2(XLXN_3),
+ .O(result));
+ AND3 XLXI_2 (.I0(XLXN_2),
+ .I1(b3),
+ .I2(b1),
+ .O(XLXN_1));
+ INV XLXI_3 (.I(b2),
+ .O(XLXN_2));
+ INV XLXI_4 (.I(b0),
+ .O(XLXN_3));
+ INV XLXI_9 (.I(b1),
+ .O(XLXN_7));
+endmodule
+`timescale 1ns / 1ps
+
+module Divide_3_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_2;
+
+ AND2 XLXI_2 (.I0(XLXN_2),
+ .I1(b3),
+ .O(result));
+ NOR3 XLXI_3 (.I0(b0),
+ .I1(b1),
+ .I2(b2),
+ .O(XLXN_2));
+endmodule
+`timescale 1ns / 1ps
+
+module Divide_0_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_1;
+ wire XLXN_2;
+ wire XLXN_3;
+ wire XLXN_4;
+ wire XLXN_5;
+ wire XLXN_6;
+
+ AND3 XLXI_1 (.I0(b3),
+ .I1(b3),
+ .I2(XLXN_2),
+ .O(XLXN_5));
+ AND2 XLXI_2 (.I0(b1),
+ .I1(XLXN_1),
+ .O(XLXN_4));
+ AND2 XLXI_3 (.I0(b1),
+ .I1(XLXN_3),
+ .O(XLXN_6));
+ INV XLXI_4 (.I(b3),
+ .O(XLXN_1));
+ INV XLXI_5 (.I(b1),
+ .O(XLXN_2));
+ INV XLXI_6 (.I(b0),
+ .O(XLXN_3));
+ OR3 XLXI_7 (.I0(XLXN_6),
+ .I1(XLXN_5),
+ .I2(XLXN_4),
+ .O(result));
+endmodule
+`timescale 1ns / 1ps
+
+module Divide_MUSER_ALU(b0,
+ b1,
+ b2,
+ b3,
+ out0,
+ out1,
+ out2,
+ out3);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output out0;
+ output out1;
+ output out2;
+ output out3;
+
+
+ Divide_1_MUSER_ALU XLXI_8 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out1));
+ Divide_2_MUSER_ALU XLXI_9 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out2));
+ Divide_3_MUSER_ALU XLXI_10 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out3));
+ Divide_0_MUSER_ALU XLXI_12 (.b0(b1),
+ .b1(b2),
+ .b2(b2),
+ .b3(b0),
+ .result(out0));
+endmodule
+`timescale 1ns / 1ps
+
+module ALU(A,
+ B,
+ C,
+ D,
+ S0,
+ S1,
+ AN0,
+ AN1,
+ AN2,
+ AN3,
+ a_out,
+ b_out,
+ c_out,
+ d_out,
+ e_out,
+ f_out,
+ g_out,
+ sign);
+
+ input A;
+ input B;
+ input C;
+ input D;
+ input S0;
+ input S1;
+ output AN0;
+ output AN1;
+ output AN2;
+ output AN3;
+ output a_out;
+ output b_out;
+ output c_out;
+ output d_out;
+ output e_out;
+ output f_out;
+ output g_out;
+ output sign;
+
+ wire XLXN_12;
+ wire XLXN_22;
+ wire XLXN_23;
+ wire XLXN_24;
+ wire XLXN_25;
+ wire XLXN_26;
+ wire XLXN_27;
+ wire XLXN_28;
+ wire XLXN_31;
+ wire XLXN_33;
+ wire XLXN_34;
+ wire XLXN_35;
+ wire XLXN_36;
+ wire XLXN_37;
+ wire XLXN_38;
+ wire XLXN_39;
+ wire XLXN_41;
+
+ Divide_MUSER_ALU XLXI_1 (.b0(D),
+ .b1(C),
+ .b2(B),
+ .b3(A),
+ .out0(XLXN_36),
+ .out1(XLXN_35),
+ .out2(XLXN_34),
+ .out3(XLXN_33));
+ Modulo_MUSER_ALU XLXI_2 (.b0(D),
+ .b1(C),
+ .b2(B),
+ .b3(A),
+ .out0(XLXN_37),
+ .out1(XLXN_38),
+ .out2(XLXN_39),
+ .out3(XLXN_41));
+ Negate_MUSER_ALU XLXI_3 (.b0(D),
+ .b1(C),
+ .b2(B),
+ .b3(A),
+ .out0(XLXN_27),
+ .out1(XLXN_28),
+ .out2(XLXN_31),
+ .out3(XLXN_26));
+ (* HU_SET = "XLXI_4_0" *)
+ M4_1E_HXILINX_ALU XLXI_4 (.D0(A),
+ .D1(XLXN_26),
+ .D2(XLXN_33),
+ .D3(XLXN_41),
+ .E(XLXN_12),
+ .S0(S0),
+ .S1(S1),
+ .O(XLXN_22));
+ (* HU_SET = "XLXI_5_1" *)
+ M4_1E_HXILINX_ALU XLXI_5 (.D0(B),
+ .D1(XLXN_27),
+ .D2(XLXN_34),
+ .D3(XLXN_39),
+ .E(XLXN_12),
+ .S0(S0),
+ .S1(S1),
+ .O(XLXN_23));
+ (* HU_SET = "XLXI_6_2" *)
+ M4_1E_HXILINX_ALU XLXI_6 (.D0(C),
+ .D1(XLXN_28),
+ .D2(XLXN_35),
+ .D3(XLXN_38),
+ .E(XLXN_12),
+ .S0(S0),
+ .S1(S1),
+ .O(XLXN_24));
+ (* HU_SET = "XLXI_7_3" *)
+ M4_1E_HXILINX_ALU XLXI_7 (.D0(D),
+ .D1(XLXN_31),
+ .D2(XLXN_36),
+ .D3(XLXN_37),
+ .E(XLXN_12),
+ .S0(S0),
+ .S1(S1),
+ .O(XLXN_25));
+ VCC XLXI_8 (.P(XLXN_12));
+ sev_seg_disp_MUSER_ALU XLXI_9 (.A(XLXN_22),
+ .B(XLXN_23),
+ .C(XLXN_24),
+ .D(XLXN_25),
+ .AN0(AN0),
+ .AN1(AN1),
+ .AN2(AN2),
+ .AN3(AN3),
+ .a_out(a_out),
+ .b_out(b_out),
+ .c_out(c_out),
+ .d_out(d_out),
+ .e_out(e_out),
+ .f_out(f_out),
+ .g_out(g_out),
+ .sign(sign));
+endmodule
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