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| author | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:19 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:19 -0500 |
| commit | 57738e75e221fe61a8f87270b430c0f1c0b8ead5 (patch) | |
| tree | 8ace7cfb1f8b7330e45dad06e4a21efeb2cadd64 /Modulo_0.vf | |
| download | ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.tar.gz ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.tar.bz2 ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.zip | |
initial commit
Diffstat (limited to 'Modulo_0.vf')
| -rwxr-xr-x | Modulo_0.vf | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/Modulo_0.vf b/Modulo_0.vf new file mode 100755 index 0000000..0b8eb41 --- /dev/null +++ b/Modulo_0.vf @@ -0,0 +1,55 @@ +////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version : 13.3
+// \ \ Application : sch2hdl
+// / / Filename : Modulo_0.vf
+// /___/ /\ Timestamp : 02/15/2012 15:00:07
+// \ \ / \
+// \___\/\___\
+//
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Modulo_0.vf" -w "X:/My Documents/ec311/lab1/Modulo_0.sch"
+//Design Name: Modulo_0
+//Device: spartan6
+//Purpose:
+// This verilog netlist is translated from an ECS schematic.It can be
+// synthesized and simulated, but it should not be modified.
+//
+`timescale 1ns / 1ps
+
+module Modulo_0(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_1;
+ wire XLXN_3;
+ wire XLXN_4;
+ wire XLXN_5;
+
+ XNOR2 XLXI_1 (.I0(b0),
+ .I1(b1),
+ .O(XLXN_1));
+ AND2 XLXI_2 (.I0(XLXN_1),
+ .I1(b2),
+ .O(XLXN_4));
+ NAND3 XLXI_3 (.I0(XLXN_5),
+ .I1(b1),
+ .I2(b2),
+ .O(XLXN_3));
+ OR2 XLXI_4 (.I0(XLXN_4),
+ .I1(XLXN_3),
+ .O(result));
+ INV XLXI_5 (.I(b0),
+ .O(XLXN_5));
+endmodule
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