diff options
| author | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:19 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:19 -0500 |
| commit | 57738e75e221fe61a8f87270b430c0f1c0b8ead5 (patch) | |
| tree | 8ace7cfb1f8b7330e45dad06e4a21efeb2cadd64 /Negate.vf | |
| download | ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.tar.gz ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.tar.bz2 ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.zip | |
initial commit
Diffstat (limited to 'Negate.vf')
| -rwxr-xr-x | Negate.vf | 203 |
1 files changed, 203 insertions, 0 deletions
diff --git a/Negate.vf b/Negate.vf new file mode 100755 index 0000000..2f68f03 --- /dev/null +++ b/Negate.vf @@ -0,0 +1,203 @@ +////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor: Xilinx
+// \ \ \/ Version : 13.3
+// \ \ Application : sch2hdl
+// / / Filename : Negate.vf
+// /___/ /\ Timestamp : 02/15/2012 15:00:10
+// \ \ / \
+// \___\/\___\
+//
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate.vf" -w "X:/My Documents/ec311/lab1/Negate.sch"
+//Design Name: Negate
+//Device: spartan6
+//Purpose:
+// This verilog netlist is translated from an ECS schematic.It can be
+// synthesized and simulated, but it should not be modified.
+//
+`timescale 1ns / 1ps
+
+module Negate_3_MUSER_Negate(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_8;
+ wire XLXN_9;
+
+ OR3 XLXI_5 (.I0(b2),
+ .I1(b1),
+ .I2(b0),
+ .O(XLXN_9));
+ NAND2 XLXI_9 (.I0(XLXN_8),
+ .I1(b3),
+ .O(result));
+ INV XLXI_12 (.I(XLXN_9),
+ .O(XLXN_8));
+endmodule
+`timescale 1ns / 1ps
+
+module Negate_1_MUSER_Negate(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_1;
+ wire XLXN_2;
+ wire XLXN_3;
+ wire XLXN_4;
+ wire XLXN_5;
+ wire XLXN_6;
+
+ AND2 XLXI_1 (.I0(b1),
+ .I1(XLXN_6),
+ .O(XLXN_2));
+ AND2 XLXI_2 (.I0(XLXN_5),
+ .I1(b0),
+ .O(XLXN_1));
+ AND3 XLXI_3 (.I0(XLXN_4),
+ .I1(XLXN_5),
+ .I2(b3),
+ .O(XLXN_3));
+ OR3 XLXI_4 (.I0(XLXN_3),
+ .I1(XLXN_1),
+ .I2(XLXN_2),
+ .O(result));
+ INV XLXI_5 (.I(b2),
+ .O(XLXN_4));
+ INV XLXI_6 (.I(b1),
+ .O(XLXN_5));
+ INV XLXI_7 (.I(b0),
+ .O(XLXN_6));
+endmodule
+`timescale 1ns / 1ps
+
+module Negate_2_MUSER_Negate(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_7;
+ wire XLXN_9;
+ wire XLXN_10;
+ wire XLXN_12;
+ wire XLXN_16;
+ wire XLXN_17;
+
+ AND2 XLXI_1 (.I0(XLXN_7),
+ .I1(b3),
+ .O(XLXN_9));
+ AND3 XLXI_2 (.I0(b2),
+ .I1(XLXN_16),
+ .I2(XLXN_17),
+ .O(XLXN_10));
+ OR2 XLXI_3 (.I0(XLXN_10),
+ .I1(XLXN_9),
+ .O(result));
+ OR3 XLXI_4 (.I0(XLXN_12),
+ .I1(b1),
+ .I2(b0),
+ .O(XLXN_7));
+ INV XLXI_5 (.I(b2),
+ .O(XLXN_12));
+ INV XLXI_6 (.I(b1),
+ .O(XLXN_16));
+ INV XLXI_7 (.I(b0),
+ .O(XLXN_17));
+endmodule
+`timescale 1ns / 1ps
+
+module Negate_0_MUSER_Negate(b0,
+ b1,
+ b2,
+ b3,
+ result);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output result;
+
+ wire XLXN_14;
+ wire XLXN_15;
+ wire XLXN_17;
+
+ AND3 XLXI_8 (.I0(b3),
+ .I1(XLXN_15),
+ .I2(XLXN_14),
+ .O(XLXN_17));
+ INV XLXI_9 (.I(b1),
+ .O(XLXN_14));
+ INV XLXI_10 (.I(b2),
+ .O(XLXN_15));
+ OR2 XLXI_12 (.I0(XLXN_17),
+ .I1(b0),
+ .O(result));
+endmodule
+`timescale 1ns / 1ps
+
+module Negate(b0,
+ b1,
+ b2,
+ b3,
+ out0,
+ out1,
+ out2,
+ out3);
+
+ input b0;
+ input b1;
+ input b2;
+ input b3;
+ output out0;
+ output out1;
+ output out2;
+ output out3;
+
+
+ Negate_0_MUSER_Negate XLXI_8 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out0));
+ Negate_1_MUSER_Negate XLXI_9 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out1));
+ Negate_2_MUSER_Negate XLXI_10 (.b0(b0),
+ .b1(b1),
+ .b2(b2),
+ .b3(b3),
+ .result(out2));
+ Negate_3_MUSER_Negate XLXI_12 (.b0(b2),
+ .b1(b1),
+ .b2(b0),
+ .b3(b3),
+ .result(out3));
+endmodule
|