initial commit

7 files changed, 105 insertions, 0 deletions

diff --git a/_xmsgs/bitgen.xmsgs b/_xmsgs/bitgen.xmsgs
new file mode 100755
index 0000000..78d5ffb
--- /dev/null
+++ b/_xmsgs/bitgen.xmsgs
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>

+<!-- IMPORTANT: This is an internal file that has been generated

+     by the Xilinx ISE software.  Any direct editing or

+     changes made to this file may result in unpredictable

+     behavior or data corruption.  It is strongly advised that

+     users do not edit the contents of this file. -->

+<messages>
+<msg type="info" file="Bitgen" num="278" delta="new" >Setting the Persist option to &quot;Yes&quot; with the CONFIG_MODE constraint value &quot;<arg fmt="%s" index="1">UnSpecified</arg>&quot; will result in the 8-bit SelectMap port being persisted.

+</msg>

+
+</messages>
+

diff --git a/_xmsgs/map.xmsgs b/_xmsgs/map.xmsgs
new file mode 100755
index 0000000..b32095a
--- /dev/null
+++ b/_xmsgs/map.xmsgs
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>

+<!-- IMPORTANT: This is an internal file that has been generated

+     by the Xilinx ISE software.  Any direct editing or

+     changes made to this file may result in unpredictable

+     behavior or data corruption.  It is strongly advised that

+     users do not edit the contents of this file. -->

+<messages>
+<msg type="info" file="MapLib" num="562" delta="new" >No environment variables are currently set.

+</msg>

+
+<msg type="info" file="LIT" num="244" delta="new" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.

+</msg>

+
+<msg type="info" file="Pack" num="1716" delta="new" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)

+</msg>

+
+<msg type="info" file="Pack" num="1720" delta="new" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)

+</msg>

+
+<msg type="info" file="Map" num="215" delta="new" >The Interim Design Summary has been generated in the MAP Report (.mrp).

+</msg>

+
+<msg type="info" file="Pack" num="1650" delta="new" >Map created a placed design.

+</msg>

+
+</messages>
+

diff --git a/_xmsgs/ngdbuild.xmsgs b/_xmsgs/ngdbuild.xmsgs
new file mode 100755
index 0000000..c42b14a
--- /dev/null
+++ b/_xmsgs/ngdbuild.xmsgs
@@ -0,0 +1,9 @@
+<?xml version="1.0" encoding="UTF-8"?>

+<!-- IMPORTANT: This is an internal file that has been generated

+     by the Xilinx ISE software.  Any direct editing or

+     changes made to this file may result in unpredictable

+     behavior or data corruption.  It is strongly advised that

+     users do not edit the contents of this file. -->

+<messages>
+</messages>
+

diff --git a/_xmsgs/par.xmsgs b/_xmsgs/par.xmsgs
new file mode 100755
index 0000000..848b12c
--- /dev/null
+++ b/_xmsgs/par.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>

+<!-- IMPORTANT: This is an internal file that has been generated

+     by the Xilinx ISE software.  Any direct editing or

+     changes made to this file may result in unpredictable

+     behavior or data corruption.  It is strongly advised that

+     users do not edit the contents of this file. -->

+<messages>
+<msg type="info" file="Par" num="282" delta="new" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;.  For best performance, set the effort level to &quot;high&quot;.

+</msg>

+
+<msg type="info" file="Par" num="459" delta="new" >The Clock Report is not displayed in the non timing-driven mode.

+</msg>

+
+</messages>
+

diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs
new file mode 100755
index 0000000..2211003
--- /dev/null
+++ b/_xmsgs/pn_parser.xmsgs
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+</messages>
+
diff --git a/_xmsgs/trce.xmsgs b/_xmsgs/trce.xmsgs
new file mode 100755
index 0000000..120dfa1
--- /dev/null
+++ b/_xmsgs/trce.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>

+<!-- IMPORTANT: This is an internal file that has been generated

+     by the Xilinx ISE software.  Any direct editing or

+     changes made to this file may result in unpredictable

+     behavior or data corruption.  It is strongly advised that

+     users do not edit the contents of this file. -->

+<messages>
+<msg type="info" file="Timing" num="2698" delta="new" >No timing constraints found, doing default enumeration.</msg>

+
+<msg type="info" file="Timing" num="2752" delta="new" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>

+
+<msg type="info" file="Timing" num="3339" delta="new" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>

+
+</messages>
+

diff --git a/_xmsgs/xst.xmsgs b/_xmsgs/xst.xmsgs
new file mode 100755
index 0000000..c99190c
--- /dev/null
+++ b/_xmsgs/xst.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>

+<!-- IMPORTANT: This is an internal file that has been generated

+     by the Xilinx ISE software.  Any direct editing or

+     changes made to this file may result in unpredictable

+     behavior or data corruption.  It is strongly advised that

+     users do not edit the contents of this file. -->

+<messages>
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">b2</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

+</msg>

+
+<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">b3</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.

+</msg>

+
+</messages>
+