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| author | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:19 -0500 |
|---|---|---|
| committer | Michael Abed <michaelabed@gmail.com> | 2012-02-16 15:46:19 -0500 |
| commit | 57738e75e221fe61a8f87270b430c0f1c0b8ead5 (patch) | |
| tree | 8ace7cfb1f8b7330e45dad06e4a21efeb2cadd64 /webtalk_pn.xml | |
| download | ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.tar.gz ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.tar.bz2 ec311-lab1-57738e75e221fe61a8f87270b430c0f1c0b8ead5.zip | |
initial commit
Diffstat (limited to 'webtalk_pn.xml')
| -rwxr-xr-x | webtalk_pn.xml | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/webtalk_pn.xml b/webtalk_pn.xml new file mode 100755 index 0000000..5409eba --- /dev/null +++ b/webtalk_pn.xml @@ -0,0 +1,47 @@ +<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pn" timeStamp="Wed Feb 15 15:16:03 2012">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="23EF1CF2DA254B0F8463C6B682ABB1F9" type="project"/>
+<property name="ProjectIteration" value="1" type="project"/>
+<property name="ProjectFile" value="X:/My Documents/ec311/lab1/lab1.xise" type="project"/>
+<property name="ProjectCreationTimestamp" value="2012-02-15T14:51:10" type="project"/>
+</section>
+<section name="Project Statistics" visible="true">
+<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
+<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
+<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
+<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
+<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
+<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
+<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
+<property name="PROP_SynthTopFile" value="changed" type="process"/>
+<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
+<property name="PROP_UseSmartGuide" value="false" type="design"/>
+<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
+<property name="PROP_intProjectCreationTimestamp" value="2012-02-15T14:51:10" type="design"/>
+<property name="PROP_intWbtProjectID" value="23EF1CF2DA254B0F8463C6B682ABB1F9" type="design"/>
+<property name="PROP_intWbtProjectIteration" value="1" type="process"/>
+<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
+<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
+<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
+<property name="PROP_xilxBitgCfg_GenOpt_ReadBack" value="true" type="process"/>
+<property name="PROP_xilxBitgStart_Clk" value="JTAG Clock" type="process"/>
+<property name="PROP_AutoTop" value="true" type="design"/>
+<property name="PROP_DevFamily" value="Spartan6" type="design"/>
+<property name="PROP_xilxBitgCfg_GenOpt_MaskFile" value="true" type="process"/>
+<property name="PROP_xilxBitgReadBk_GenBitStr" value="true" type="process"/>
+<property name="PROP_DevDevice" value="xc6slx16" type="design"/>
+<property name="PROP_DevFamilyPMName" value="spartan6" type="design"/>
+<property name="PROP_DevPackage" value="csg324" type="design"/>
+<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
+<property name="PROP_DevSpeed" value="-3" type="design"/>
+<property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
+<property name="FILE_SCHEMATIC" value="16" type="source"/>
+<property name="FILE_UCF" value="1" type="source"/>
+</section>
+</application>
+</document>
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