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+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+ <!-- -->
+
+ <!-- For tool use only. Do not edit. -->
+
+ <!-- -->
+
+ <!-- ProjectNavigator created generated project file. -->
+
+ <!-- For use in tracking generated file and other information -->
+
+ <!-- allowing preservation of process status. -->
+
+ <!-- -->
+
+ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
+
+ <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+ <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="lab1.xise"/>
+
+ <files xmlns="http://www.xilinx.com/XMLSchema">
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="ALU.bld"/>
+ <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="ALU.cmd_log"/>
+ <file xil_pn:fileType="FILE_JHD" xil_pn:name="ALU.jhd"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="ALU.lso"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="ALU.ncd" xil_pn:subbranch="Par"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="ALU.ngc"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="ALU.ngd"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="ALU.ngr"/>
+ <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="ALU.pad"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="ALU.par" xil_pn:subbranch="Par"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="ALU.pcf" xil_pn:subbranch="Map"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ALU.prj"/>
+ <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="ALU.ptwx"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="ALU.stx"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="ALU.syr"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="ALU.twr" xil_pn:subbranch="Par"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="ALU.twx" xil_pn:subbranch="Par"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="ALU.unroutes" xil_pn:subbranch="Par"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="ALU.ut" xil_pn:subbranch="FPGAConfiguration"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="ALU.vf"/>
+ <file xil_pn:fileType="FILE_XPI" xil_pn:name="ALU.xpi"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="ALU.xst"/>
+ <file xil_pn:fileType="FILE_NCD" xil_pn:name="ALU_guide.ncd" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="ALU_map.map" xil_pn:subbranch="Map"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="ALU_map.mrp" xil_pn:subbranch="Map"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="ALU_map.ncd" xil_pn:subbranch="Map"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="ALU_map.ngm" xil_pn:subbranch="Map"/>
+ <file xil_pn:fileType="FILE_XRPT" xil_pn:name="ALU_map.xrpt"/>
+ <file xil_pn:fileType="FILE_XRPT" xil_pn:name="ALU_ngdbuild.xrpt"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="ALU_pad.csv" xil_pn:subbranch="Par"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="ALU_pad.txt" xil_pn:subbranch="Par"/>
+ <file xil_pn:fileType="FILE_XRPT" xil_pn:name="ALU_par.xrpt"/>
+ <file xil_pn:fileType="FILE_HTML" xil_pn:name="ALU_summary.html"/>
+ <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="ALU_summary.xml"/>
+ <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="ALU_usage.xml"/>
+ <file xil_pn:fileType="FILE_XRPT" xil_pn:name="ALU_xst.xrpt"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Divide.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Divide.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Divide_0.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Divide_0.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Divide_1.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Divide_1.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Divide_2.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Divide_2.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Divide_3.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Divide_3.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Modulo.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Modulo.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Modulo_0.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Modulo_0.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Modulo_1.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Modulo_1.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Modulo_3.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Modulo_3.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Negate.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Negate.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Negate_0.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Negate_0.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Negate_1.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Negate_1.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Negate_2.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Negate_2.vf"/>
+ <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="Negate_3.sym" xil_pn:origination="imported"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="Negate_3.vf"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
+ <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="alu.bgn" xil_pn:subbranch="FPGAConfiguration"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="alu.bit" xil_pn:subbranch="FPGAConfiguration"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="alu.drc" xil_pn:subbranch="FPGAConfiguration"/>
+ <file xil_pn:fileType="FILE_MSK" xil_pn:name="alu.msk"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
+ <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="sev_seg_disp.vf"/>
+ <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
+ <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
+ <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
+ <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
+ </files>
+
+ <transforms xmlns="http://www.xilinx.com/XMLSchema">
+ <transform xil_pn:end_ts="1329336136" xil_pn:name="TRANEXT_compLibraries_FPGA" xil_pn:prop_ck="1321705353062746806" xil_pn:start_ts="1329336136">
+ <status xil_pn:value="FailedRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336925" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1329336925">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336928" xil_pn:in_ck="-1529285955265280609" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="-1120318093780454153" xil_pn:start_ts="1329336925">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForInputs"/>
+ <status xil_pn:value="InputChanged"/>
+ <outfile xil_pn:name="ALU.vf"/>
+ <outfile xil_pn:name="Divide.vf"/>
+ <outfile xil_pn:name="Divide_0.vf"/>
+ <outfile xil_pn:name="Divide_1.vf"/>
+ <outfile xil_pn:name="Divide_2.vf"/>
+ <outfile xil_pn:name="Divide_3.vf"/>
+ <outfile xil_pn:name="Modulo.vf"/>
+ <outfile xil_pn:name="Modulo_0.vf"/>
+ <outfile xil_pn:name="Modulo_1.vf"/>
+ <outfile xil_pn:name="Modulo_3.vf"/>
+ <outfile xil_pn:name="Negate.vf"/>
+ <outfile xil_pn:name="Negate_0.vf"/>
+ <outfile xil_pn:name="Negate_1.vf"/>
+ <outfile xil_pn:name="Negate_2.vf"/>
+ <outfile xil_pn:name="Negate_3.vf"/>
+ <outfile xil_pn:name="sev_seg_disp.vf"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336928" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-4992524107072518650" xil_pn:start_ts="1329336928">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336928" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1329336928">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336928" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-1217049267018461767" xil_pn:start_ts="1329336928">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336928" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="1106364426758808884" xil_pn:start_ts="1329336928">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336928" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-4186483203912133424" xil_pn:start_ts="1329336928">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336941" xil_pn:in_ck="-5492412754742126177" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-819365665305975787" xil_pn:start_ts="1329336928">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="WarningsGenerated"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="ALU.jhd"/>
+ <outfile xil_pn:name="ALU.lso"/>
+ <outfile xil_pn:name="ALU.ngc"/>
+ <outfile xil_pn:name="ALU.ngr"/>
+ <outfile xil_pn:name="ALU.prj"/>
+ <outfile xil_pn:name="ALU.stx"/>
+ <outfile xil_pn:name="ALU.syr"/>
+ <outfile xil_pn:name="ALU.xst"/>
+ <outfile xil_pn:name="ALU_xst.xrpt"/>
+ <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
+ <outfile xil_pn:name="webtalk_pn.xml"/>
+ <outfile xil_pn:name="xst"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336941" xil_pn:in_ck="87022295022" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="3734212952555236" xil_pn:start_ts="1329336941">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336948" xil_pn:in_ck="958840011568711062" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-1233222934028612217" xil_pn:start_ts="1329336941">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <outfile xil_pn:name="ALU.bld"/>
+ <outfile xil_pn:name="ALU.ngd"/>
+ <outfile xil_pn:name="ALU_ngdbuild.xrpt"/>
+ <outfile xil_pn:name="_ngo"/>
+ <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336962" xil_pn:in_ck="958840054187154039" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1463976855095865663" xil_pn:start_ts="1329336948">
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+ <status xil_pn:value="ReadyToRun"/>
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+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="ALU.pcf"/>
+ <outfile xil_pn:name="ALU_map.map"/>
+ <outfile xil_pn:name="ALU_map.mrp"/>
+ <outfile xil_pn:name="ALU_map.ncd"/>
+ <outfile xil_pn:name="ALU_map.ngm"/>
+ <outfile xil_pn:name="ALU_map.xrpt"/>
+ <outfile xil_pn:name="ALU_summary.xml"/>
+ <outfile xil_pn:name="ALU_usage.xml"/>
+ <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336993" xil_pn:in_ck="5688090717086154096" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1178055513630676559" xil_pn:start_ts="1329336962">
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+ <status xil_pn:value="ReadyToRun"/>
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+ <outfile xil_pn:name="ALU.pad"/>
+ <outfile xil_pn:name="ALU.par"/>
+ <outfile xil_pn:name="ALU.ptwx"/>
+ <outfile xil_pn:name="ALU.unroutes"/>
+ <outfile xil_pn:name="ALU.xpi"/>
+ <outfile xil_pn:name="ALU_pad.csv"/>
+ <outfile xil_pn:name="ALU_pad.txt"/>
+ <outfile xil_pn:name="ALU_par.xrpt"/>
+ <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
+ </transform>
+ <transform xil_pn:end_ts="1329337024" xil_pn:in_ck="87022287397" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="8036697451854927384" xil_pn:start_ts="1329336993">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
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+ <status xil_pn:value="OutOfDateForOutputs"/>
+ <status xil_pn:value="OutputChanged"/>
+ <outfile xil_pn:name="ALU.ut"/>
+ <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+ <outfile xil_pn:name="alu.bgn"/>
+ <outfile xil_pn:name="alu.bit"/>
+ <outfile xil_pn:name="alu.drc"/>
+ <outfile xil_pn:name="alu.msk"/>
+ <outfile xil_pn:name="usage_statistics_webtalk.html"/>
+ <outfile xil_pn:name="webtalk.log"/>
+ <outfile xil_pn:name="webtalk_pn.xml"/>
+ </transform>
+ <transform xil_pn:end_ts="1329337061" xil_pn:in_ck="129639531599" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="2682241697568822907" xil_pn:start_ts="1329337061">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ </transform>
+ <transform xil_pn:end_ts="1329336993" xil_pn:in_ck="958834428552681075" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1329336985">
+ <status xil_pn:value="SuccessfullyRun"/>
+ <status xil_pn:value="ReadyToRun"/>
+ <status xil_pn:value="OutOfDateForPredecessor"/>
+ <outfile xil_pn:name="ALU.twr"/>
+ <outfile xil_pn:name="ALU.twx"/>
+ <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
+ </transform>
+ </transforms>
+
+</generated_project>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-04 18:40:06 +0000