finish itHEADmaster

1 files changed, 27 insertions, 0 deletions

diff --git a/_xmsgs/map.xmsgs b/_xmsgs/map.xmsgs
new file mode 100755
index 0000000..4ecf2a7
--- /dev/null
+++ b/_xmsgs/map.xmsgs
@@ -0,0 +1,27 @@
+<?xml version="1.0" encoding="UTF-8"?>

+<!-- IMPORTANT: This is an internal file that has been generated

+     by the Xilinx ISE software.  Any direct editing or

+     changes made to this file may result in unpredictable

+     behavior or data corruption.  It is strongly advised that

+     users do not edit the contents of this file. -->

+<messages>
+<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.

+</msg>

+
+<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.

+</msg>

+
+<msg type="info" file="Pack" num="1716" delta="old" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)

+</msg>

+
+<msg type="info" file="Pack" num="1720" delta="old" >Initializing voltage to <arg fmt="%0.3f" index="1">1.140</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">1.140</arg> to <arg fmt="%0.3f" index="3">1.260</arg> Volts)

+</msg>

+
+<msg type="info" file="Map" num="215" delta="old" >The Interim Design Summary has been generated in the MAP Report (.mrp).

+</msg>

+
+<msg type="info" file="Pack" num="1650" delta="old" >Map created a placed design.

+</msg>

+
+</messages>
+