finish itHEADmaster

1 files changed, 143 insertions, 36 deletions

diff --git a/planAhead_run_1/planAhead.log b/planAhead_run_1/planAhead.log
index 469ec29..bceaf51 100644..100755
--- a/planAhead_run_1/planAhead.log
+++ b/planAhead_run_1/planAhead.log
@@ -1,28 +1,31 @@
 #-----------------------------------------------------------
-# PlanAhead v13.4 (64-bit)
-# Build 157570 by hdbuild on Fri Dec 16 12:49:33 MST 2011
-# Start of session at: Wed Feb 15 21:35:38 2012
-# Process ID: 29568
-# Log file: /home/michael/Documents/School/EC311/lab2/planAhead_run_1/planAhead.log
-# Journal file: /home/michael/Documents/School/EC311/lab2/planAhead_run_1/planAhead.jou
+# PlanAhead v13.3 (64-bit)
+# Build 147507 by hdbuild on Tue Oct  4 19:13:50 MDT 2011
+# Start of session at: Thu Feb 16 20:00:27 2012
+# Process ID: 3200
+# Log file: X:/My Documents/ec311/ec311-lab2/planAhead_run_1/planAhead.log
+# Journal file: X:/My Documents/ec311/ec311-lab2/planAhead_run_1/planAhead.jou
 #-----------------------------------------------------------
 INFO: [Common-78] Attempting to get a license: PlanAhead
 INFO: [Common-82] Got a license: PlanAhead
-INFO: [Device-25] Loading parts and site information from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/arch.xmlParsing RTL primitives file [/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml]
-Finished parsing RTL primitives file [/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml]
+INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
 start_gui
-source /home/michael/Documents/School/EC311/lab2/pa.fromHdl.tcl
-# create_project -name lab2 -dir "/home/michael/Documents/School/EC311/lab2/planAhead_run_2" -part xc6slx16csg324-3
-Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/verilog.xml].
-Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/verilog.xml].
-Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/vhdl.xml].
-Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/vhdl.xml].
-Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/ucf.xml].
-Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/ucf.xml].
+source {X:/My Documents/ec311/ec311-lab2/pa.fromHdl.tcl}
+# create_project -name lab2 -dir "X:/My Documents/ec311/ec311-lab2/planAhead_run_2" -part xc6slx16csg324-3
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
+create_project: Time (s): 17.940w.  Memory (MB): 522.531p 21.227g
 # set_param project.pinAheadLayout yes
 # set srcset [get_property srcset [current_run -impl]]
+# set_property top ALUSHOW $srcset
 # set_property target_constrs_file "ALUSHOW.ucf" [current_fileset -constrset]
-Adding file '/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf' to fileset 'constrs_1'
+Adding file 'X:\My Documents\ec311\ec311-lab2\ALUSHOW.ucf' to fileset 'constrs_1'
+CRITICAL WARNING: [Designutils-735] The top module "ALUSHOW" specified for this project can not be validated. The current project is using automatic hierarchy update mode, and hence a new suitable replacement top will be automatically selected. If this is not desired, please change the hierarchy update mode to one of the manual compile order modes first, and then set top to any desired value.
 # set hdlfile [add_files [list {sev_seg_disp.vf}]]
 # set_property file_type Verilog $hdlfile
 # set_property library work $hdlfile
@@ -32,26 +35,130 @@ Adding file '/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf' to fileset '
 # set hdlfile [add_files [list {ALUSHOW.vf}]]
 # set_property file_type Verilog $hdlfile
 # set_property library work $hdlfile
-# set_property top ALUSHOW $srcset
 # add_files [list {ALUSHOW.ucf}] -fileset [get_property constrset [current_run]]
 # open_rtl_design -part xc6slx16csg324-3
 INFO: [PlanAhead-58] Using Verific elaboration
-Parsing VHDL file "/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify
-Analyzing Verilog file "/home/michael/Documents/School/EC311/lab2/ALU.v" into library work
-Analyzing Verilog file "/home/michael/Documents/School/EC311/lab2/ALUSHOW.vf" into library work
-CRITICAL WARNING: [EDIF-96] Could not resolve non-primitive black box cell 'ALU' defined in file 'ALU.v' instantiated as 'XLXI_4'.
-Loading clock regions from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
-Loading clock buffers from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
-Loading package pin functions from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/PinFunctions.xml...
-Loading package from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
-Loading io standards from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/./parts/xilinx/spartan6/IOStandards.xml
-Loading device configuration modes from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/ConfigModes.xml
-Loading list of drcs for the architecture : /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/./parts/xilinx/spartan6/drc.xml
-Parsing UCF File [/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf]
-Finished Parsing UCF File [/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf]
+Parsing VHDL file "C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
+Analyzing Verilog file "X:\My Documents\ec311\ec311-lab2\ALU.v" into library work
+Analyzing Verilog file "X:\My Documents\ec311\ec311-lab2\ALUSHOW.vf" into library work
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab2\ALUSHOW.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab2\ALUSHOW.ucf]
 INFO: [PlanAhead-566] Unisim Transformation Summary:
-No Unisim elements were transformed.open_rtl_design: Time (s): 20.520u 0.570s 28.760w. Memory (MB): 4537.992p 149.031g
-exit
-stop_gui
-INFO: [PlanAhead-261] Exiting PlanAhead...
-INFO: [Common-83] Releasing license: PlanAhead
+No Unisim elements were transformed.open_rtl_design: Time (s): 20.358w.  Memory (MB): 740.285p 214.488g
+startgroup
+startgroup
+set_property loc PAD178 [get_ports {A[3]}]
+set_property loc PAD178 [get_ports {A[3]}]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD164 [get_ports {A[2]}]
+set_property loc PAD164 [get_ports {A[2]}]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD163 [get_ports {A[1]}]
+set_property loc PAD163 [get_ports {A[1]}]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD162 [get_ports {A[0]}]
+set_property loc PAD162 [get_ports {A[0]}]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD154 [get_ports {S[0]}]
+set_property loc PAD154 [get_ports {S[0]}]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD159 [get_ports {S[1]}]
+set_property loc PAD159 [get_ports {S[1]}]
+endgroup
+endgroup
+save_design
+startgroup
+startgroup
+set_property loc PAD112 [get_ports AN0]
+set_property loc PAD112 [get_ports AN0]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD111 [get_ports AN1]
+set_property loc PAD111 [get_ports AN1]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD110 [get_ports AN2]
+set_property loc PAD110 [get_ports AN2]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD109 [get_ports AN3]
+set_property loc PAD109 [get_ports AN3]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD113 [get_ports ao]
+set_property loc PAD113 [get_ports ao]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD114 [get_ports bo]
+set_property loc PAD114 [get_ports bo]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD115 [get_ports co]
+set_property loc PAD115 [get_ports co]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD116 [get_ports do]
+set_property loc PAD116 [get_ports do]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD117 [get_ports eo]
+set_property loc PAD117 [get_ports eo]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD118 [get_ports fo]
+set_property loc PAD118 [get_ports fo]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD119 [get_ports go]
+set_property loc PAD119 [get_ports go]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD120 [get_ports sign]
+set_property loc PAD120 [get_ports sign]
+endgroup
+endgroup
+save_design